NDLI: Device and Circuit Performance Estimation of Junctionless Bulk FinFETs

Content Provider	IEEE Xplore Digital Library
Author	Ming-Hung Han Chun-Yen Chang Hung-Bin Chen Ya-Chi Cheng Yung-Chun Wu
Copyright Year	1963
Abstract	The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (V_th) roll-off characteristics at supply voltage (V_DD) 1 V. Analyses of electron density and electricfield distributions in on-state and off-state also show that the JL devices have better on-off current ratios. Regarding design aspects, the effects of channel doping concentration (N_ch) and Fin height (H)/width (W) on device V_th are also compared. In addition, the V_th of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (N_sub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (t_HL) and low-to-high delay time (t_LH) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.
Sponsorship	IEEE Electron Devices Society
Starting Page	1807
Ending Page	1813
Page Count	7
File Size	946326
File Format	PDF
ISSN	00189383
Volume Number	60
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FinFETs Doping Logic gates Integrated circuit modeling Threshold voltage Inverters Mathematical model static random access memory (SRAM) 3-D simulation FinFET inverter circuit junctionless short channel
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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