NDLI: A New Programming Scheme for the Improvement of Program Disturb Characteristics in Scaled nand Flash Memory

Content Provider	IEEE Xplore Digital Library
Author	Shirota, R. Chen-Hao Huang Nagai, S. Sakamoto, Y. Fu-Hai Li Mitiukhina, N. Arakawa, H.
Copyright Year	1963
Abstract	This paper investigates the new programming scheme to reduce the program disturb in the NAND Flash memory. Program disturb characteristics are determined by the unwilling electron injections in the floating gate of the unselected cells during programming. Thus, the key point to improve the program disturb characteristics is how to suppress the electron injection in the unselected cells. This requirement can be implemented by reducing the number of electrons in the unselected NAND strings prior to programming. By applying negative bias to all the word lines in the selected block, excess electrons can be removed from the channel and source/drain regions into the bit line or the source line using drift and diffusion mechanisms, and also electrons in the surface states can be recombined with accumulated holes before programming. After the pretreatment of electron reduction in the NAND string, a normal NAND program sequence follows. The advantage of the pretreatment before programming has been verified by measuring the 8-Gb NAND Flash memory with a 50-nm technology node. Significant reduction of the threshold voltage shift was observed even after the severe program disturb stress, which corresponds to around 30 times of the programming of the 2 bit/cell operation.
Sponsorship	IEEE Electron Devices Society
Starting Page	2767
Ending Page	2773
Page Count	7
File Size	1025897
File Format	PDF
ISSN	00189383
Volume Number	59
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Programming Stress Electric potential Charge carrier processes Boosting Flash memory IEEE Potentials surface state Fowler–Nordheim (FN) tunneling junction leakage (J/L) nand cell program disturb select gate (SG)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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