NDLI: Fabrication and Testing of a Wafer-Level Vacuum Package for MEMS Device

Content Provider	IEEE Xplore Digital Library
Author	Premachandran, C.S. Ser Choong Chong Liw, S. Nagarajan, R.
Copyright Year	1999
Abstract	A wafer-level vacuum package with getters deposited on the cap wafer is developed for an accelerometer device. An accelerometer wafer and cap wafer is bonded together in a vacuum of 1 mtorr and is characterized using a micro-electro-mechanical systems (MEMS) motion analyzer (MMA). Vacuum inside the package is measured indirectly by measuring the Q-factor response of the accelerometer structure inside the package. The obtained results indicated that there is variation from the center to the edge of the wafer. This may be due to difference in the outgassing of the package. Different reliability tests on the wafer-level package showed the package is robust to the reliability conditions. A progressive test on the Q-factor for different cycles of reliability test proved that there is no shift in the measurement value. A 3-D wafer-level package for accelerometer device is also developed to meet the requirements of vacuum packaging. Hermeticity and CV test showed no degradation in the device performance when subjected to reliability tests.
Sponsorship	IEEE Components, Packaging, and Manufacturing Technology Society IEEE Components, Packaging and Manufacturing Technology Society
Starting Page	486
Ending Page	490
Page Count	5
File Size	801846
File Format	PDF
ISSN	15213323
Volume Number	32
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication Testing Wafer scale integration Packaging Microelectromechanical devices Accelerometers Q measurement Gettering Wafer bonding Vacuum systems wafer-level package Micro-electro-mechanical systems (MEMS) outgassing three-dimensional (3-D) SIP through silicon via vacuum package
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in