NDLI: An Automated Approach to Estimating Hardness Assurance Issues in Triple-Modular Redundancy Circuits in Xilinx FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Quinn, H. Graham, P. Pratt, B.
Copyright Year	1963
Abstract	The Xilinx Virtex family of static random access memory (SRAM) based field programmable gate array (FPGA) devices have made inroads into space-based computational platforms over the past decade. These devices are well-suited for digital signal processing (DSP) algorithms that are often used on orbit, providing the speedup of custom hardware without the cost of fabricating an application-specific integrated circuit (ASIC). SRAM FPGAs store the circuit in radiation-tolerant SRAM and SEUs can affect both the circuit functionality and the circuit state. Triple-modular redundancy (TMR) can be used to mask SEUs so that malfunctioning circuitry will not affect the output data. Unfortunately, applying TMR to a user circuit is difficult and unprotected cross-section is possible due to problems with the circuit design, device constraints, or the implementation of the user circuit on the FPGA. Given the complexity of these designs, estimating hardness assurance issues is not simple. This paper will present a tool, called the scalable tool for the analysis of reliable circuits (STARC), that can automatically estimate unprotected cross-section and other hardness assurance issues for TMR-protected circuits.
Sponsorship	IEEE Nuclear and Plasma Sciences Society Computer Applications in Nuclear and Plasma Sciences (CANPS) Lawrence Berkeley Lab. Lawrence Livermore Nat. Lab. APS College of William and Mary Continuous Electron Beam Accelerator Facility NASA Defence Nuclear Agency Sandia National Laboratories Jet Propulsion Laboratory Brookhaven Nat. Lab. Lawrence Livermore Nat. Lab IEEE/NPPS Radiat. Effects Committee Defence Nuclear Agency/DoD Sandia National Laboratories/DOE Jet Propulsion Laboratory/NASA Phillips Lab./DoD
Starting Page	3070
Ending Page	3076
Page Count	7
File Size	154012
File Format	PDF
ISSN	00189499
Volume Number	55
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Random access memory Redundancy Digital signal processing Application specific integrated circuits Single event transient SRAM chips Signal processing algorithms Hardware Costs reliability analysis Fault identification
Content Type	Text
Resource Type	Article
Subject	Nuclear and High Energy Physics Electrical and Electronic Engineering Nuclear Energy and Engineering

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An Analysis Based on Fault Injection of Hardening Techniques for SRAM-Based FPGAs

Domain Crossing Errors: Limitations on Single Device Triple-Modular Redundancy Circuits in Xilinx FPGAs

Fine-Grain SEU Mitigation for FPGAs Using Partial TMR

Neutron Cross-Section of N-Modular Redundancy Technique in SRAM-Based FPGAs

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Soft Errors in SRAM-FPGAs: A Comparison of Two Complementary Approaches

Time Multiplexed Triple Modular Redundancy for Single Event Upset Mitigation

An Automated Approach to Estimating Hardness Assurance Issues in Triple-Modular Redundancy Circuits in Xilinx FPGAs

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