NDLI: Proceedings of the 2008 international symposium on Low Power Electronics & Design (ISLPED '08)

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Increasing minimum operating voltage $(V_{DDmin})$ with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators

Low power design under parameter variations

3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding

Entry control in network-on-chip for memory power reduction

$O^{2}C:$ occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors

Power delivery for high performance microprocessors

Energy-efficient MESI cache coherence with pro-active snoop filtering for multicore microprocessors

Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies

Expected system energy consumption minimization in leakage-aware DVS systems

Full-system chip multiprocessor power evaluations using FPGA-based emulation

On leakage currents: sources and reduction for transistors, gates, memories and digital systems

Instruction-driven clock scheduling with glitch mitigation

System implications of integrated photonics

Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology

Power-gating-aware high-level synthesis

Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion

Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation

Thermal analysis of 8-T SRAM for nano-scaled technologies

Energy conservation by adaptive feature loading for mobile content-based image retrieval

PowerAntz: distributed power sharing strategy for network on chip

Low power high bandwidth amplifier with RC Miller and gain enhanced feedforward compensation

A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes

On the power efficiency of cascode compensation over Miller compensation in two-stage operational amplifiers

Hybrid dynamic thermal management based on statistical characteristics of multimedia applications

Noninvasive leakage power tomography of integrated circuits by compressive sensing

Thread fusion

Innovations to extend CMOS nano-transistors to the limit

Enhancing beneficial jitter using phase-shifted clock distribution

A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing

Low-power high-accuracy timing systems for efficient duty cycling

Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power

Analyzing static and dynamic write margin for nanometer SRAMs

Extending the lifetime of media recorders constrained by battery and flash memory size

Single stage static level shifter design for subthreshold to I/O voltage conversion

A secure and low-energy logic style using charge recovery approach

A 1-V piecewise curvature-corrected CMOS bandgap reference

Power-efficient clustering via incomplete bypassing

Advances in low power verification

Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction

Variation-aware gate sizing and clustering for post-silicon optimized circuits

Power reduction in on-chip interconnection network by serialization

Word-interleaved cache: an energy efficient data cache architecture

A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning

Lazy instruction scheduling: keeping performance, reducing power

On the rules of low-power design (and how to break them)

A probabilistic technique for full-chip leakage estimation

Next-generation power-aware design

Bus encoding for simultaneous delay and energy optimization

Frequency planning for multi-core processors under thermal constraints

Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits

Variability of flip-flop timing at sub-threshold voltages

Low power current mode receiver with inductive input impedance

Analytical results for design space exploration of multi-core processors employing thread migration

A physical level study and optimization of CAM-based checkpointed register alias table

Proceedings of the 2008 international symposium on Low Power Electronics & Design (ISLPED '08)

Content Provider	ACM Digital Library
Editor	Keshavarzi, Ali Austin, Todd Oklobdzija, Vojin G. Irwin, Mary Jane Ravikumar, C. P. Tsui, Chi-Ying Amrutur, Bharadwaj Mahapatra, Rabi N. Pangrle, Barry Bindal, Niraj Erraguntla, Vasantha Azadet, Kameran Bhunia, Swarup Kondu, Masaaki Henkel, Joerg Suzuki, Hiroaki Narayanan, Vijaykrishnan Nebel, Wolfgang
Copyright Year	2008
Abstract	Welcome to the 13th ACM/IEEE International Symposium on Low Power Electronics and Design! The 2008 edition of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) welcomes you to Bangalore, India also known as "The Silicon Valley of India." The conference is hosted by Indian Institute of Science which is celebrating its centennial year. On a par with this great location, a strong and diverse technical program features six plenary talks from leaders in the field plus another embedded invited talk, two evening panel sessions as well as six embedded tutorials. On the first day, Jaswinder Ahuja, Corporate VP, Cadence and Chairman of India Semiconductor Association, will deliver a talk about a collaborative approach towards a green electronic world. The evening session on Monday will feature a distinguished panel of guests discussing the tradeoffs and costs in achieving power reduction in designs. The morning plenary talk on Tuesday will feature Norm Jouppi HP Fellow and Director of the Exascale Computing Lab speaking about the system implications of integrated photonics. The afternoon plenary talk will be delivered by Tahir Ghani, Intel Fellow and Director of Transistor Technology and Integration. His talk will cover innovations to extend CMOS transistors to the limit. The evening panel session features another selection of distinguished panelists to discuss where the next 100x in power improvements are going to come from in multi-core designs. The first plenary talk on Wednesday will be delivered by Janick Bergeron, Synopsys Fellow, on advances in low power verification. The first afternoon plenary talk on Wednesday will be given by Professor Todd Austin and he will be speaking on the rules of low power design and how to successfully break them. The final plenary session of the conference will be delivered by Professor Takayasu Sakurai. His talk will be on next the generation of low power designs and systems. Out of 159 submissions received, 63 strong technical papers were accepted for presentation in paper or poster sessions, yielding an acceptance rate of 31% for regular and short papers (50 papers), or 40% including 13 posters. Topics range from low power technology, circuits, and memory; low voltage analog and RF design; power aware design and tools; power efficient architecture techniques; and system and application level power optimization. The program is organized into twelve technical sessions featuring long (30 min) and short (20 min) paper presentations, as well as one interactive poster sessions that will provide an additional venue for authors and symposium attendees to interact in an informal setting. Following the tradition of ISLPED, this year's event also includes exhibits featuring tools and methodologies from leading vendors of low power or power-aware design tools. The program also includes an industry session that contains an invited talk and a tutorial with presenters from companies participating in ISLPED. Winning entries to the annual Low Power Design Contest will also be featured in a separate technical session. Such a rich and strong program would have not been possible without the help of an outstanding Technical Program Committee who has worked for weeks reviewing and selecting the best papers. Our many thanks go to the 2008 ISLPED officers who have made everything work like clockwork: Ali Keshavarzi and Joerg Henkel, general vice-chairs; Bharadwaj Amrutur, Local Arrangements; Yuan Xie, Treasurer; Qing Wu and Vasantha Erraguntla, Exhibits; Poras Balsara, Yu Cao, Design Contest; Farzan Fallah, Shaleen Babu, Publicity, Yung-Hsiang Lu, Web Chair. Partha Ranganthan, Panels and Prasanth Mangalagiri, Submissions. We express our special thanks to Prof. Govindarajan, Ms. Chaitra Rajeevalochana and student volunteers from IISc for local arrangements.
Related Links	http://computer.org/proceedings/islped/2008/8109
ISBN	9781605581095
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-08-11
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

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