NDLI: An Efficient Approach to Sample On-Chip Power Supplies

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An Efficient Approach to Sample On-Chip Power Supplies

Content Provider	ACM Digital Library
Author	Khatri, Sunil P. Murray, Luke
Abstract	In recent years, post-silicon debugging has become a significantly difficult exercise due to the increase in the size of the electrical state of the IC being debugged, coupled with the limited fraction of this state that is visible to the debug engineer. As the number of transistors increases, the number of possible electrical states increases exponentially, while the amount of information that can be accessed grows at a much slower rate. This difficulty is compounded by the outsourcing of IP blocks, which creates more black boxes that the debug engineer must work around. As a result, when an IC fails tracking down the cause of the failure becomes a monumental task, and debugging becomes more art than science. One source of errors in a test circuit is the fluctuation of the power supplies during a single clock cycle. These supply variations can increase or decrease the speed of a circuit and lead to errors such as hold time violations and setup time violations. This paper presents a circuit that samples precisely the power supply multiple times in a clock cycle, allowing the debug engineer to quantify the variations in the supply over a clock cycle. With this information, a better understanding of the electrical state of the test chip is made possible. The circuit presented in this paper can sample the supply voltage with a quantization of 0.291mV, and the output is linear with an $R^{2}$ value of 0.9987.
Starting Page	241
Ending Page	244
Page Count	4
File Format	PDF
ISBN	9781450334747
DOI	10.1145/2742060.2742121
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-05-20
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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