NDLI: DimNoC: a dim silicon approach towards power-efficient on-chip network

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DimNoC: a dim silicon approach towards power-efficient on-chip network

Content Provider	ACM Digital Library
Author	Ouyang, Jin Xie, Yuan Zhan, Jia Zhao, Jishen Ge, Fen
Abstract	The diminishing momentum of Dennard scaling leads to the ever increasing power density of integrated circuits, and a decreasing portion of transistors on a chip that can be switched on simultaneously---a problem recently discovered and known as dark silicon. There has been innovative work to address the "dark silicon" problem in the fields of power-efficient core and cache system. However, dark silicon challenges with Network-on-Chip (NoC) are largely unexplored. To address this issue, we propose DimNoC, a "dim silicon" approach, which leverages drowsy SRAM and STT-RAM technologies to replace pure SRAM-based NoC buffers. Specifically, we propose two novel hybrid buffer architectures: 1) a Hierarchical Buffer (HB) architecture, which divides the input buffers into a hierarchy of levels with different memory technologies operating at various power states; 2) a Banked Buffer (BB) architecture, which organizes drowsy SRAM and STT-RAM into separate banks in order to hide the long write-latency of STT-RAM. Our experiments show that the proposed DimNoC can achieve 30.9% network energy saving, 20.3% energy-delay product (EDP) reduction, and 7.6% router area decrease compared with the baseline SRAM-based NoC design.
Starting Page	1
Ending Page	6
Page Count	6
File Format	PDF
ISBN	9781450335201
DOI	10.1145/2744769.2744824
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-06-07
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Stt-ram Network-on-chip Dark silicon
Content Type	Text
Resource Type	Article

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