NDLI: Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding

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Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding

Content Provider	ACM Digital Library
Author	Cotofana, Sorin Marconi, Thomas
Abstract	Stochastic Computing (SC) is an attractive solution for implementing Low Density Parity Codes (LDPC) decoders due to its fault tolerance capability and low hardware requirements. However, in practical implementations, SC efficiency is limited by the Stochastic Bitstream (SB) length and by the computation inaccuracies due to non-unique SB representations. In this paper, rather than statically fixing the SB length at run-time, we propose a Dynamic Bitstream Length Scaling (DBLS) technique, which adjusts on-the-fly the SB length such that Quality of Service requirements for energy efficient LDPC decoding are fulfilled. In this way, depending on the communication channel condition, different SB lengths are adaptively utilized such that the best decoding performance vs energy consumption tradeoff is achieved. To evaluate the DBLS practical implications we selected an (1296,648) LDPC with $d_{v}=3$ and $d_{c}=6$ and implemented our approach and the best state-of-the-art stochastic LDPC decoder with 64-bit edge memory on a Virtex-7 FPGA. Experimental results indicate that our proposal requires 9% more FFs and 3% more LUTs while diminishing the energy consumption by 31-80% and providing 1.5-5.1x higher throughput.
Starting Page	245
Ending Page	248
Page Count	4
File Format	PDF
ISBN	9781450334747
DOI	10.1145/2742060.2742117
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-05-20
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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