NDLI: On the Functions Realized by Stochastic Computing Circuits

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Digital Microfluidic Biochips: Towards Functional Diversity, More than Moore, and Cyberphysical Integration

Efficient Test Application for Rapid Multi-Temperature Testing

Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICs

Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing

Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores

Phase-based Cache Locking for Embedded Systems

Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures

Computational Thinking Meets Design Thinking: Technology and Arts Collaborations

Graphene Neural Sensors for Next Generation In Vivo Imaging and Optogenetics

Online and Operand-Aware Detection of Failures Utilizing False Alarm Vectors

Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis

EDA Challenges for Memristor-Crossbar based Neuromorphic Computing

Origami: A Convolutional Network Accelerator

Space Oblivious Compression: Power Reduction for Non-Volatile Main Memories

Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks

Recent Advances in Brain-controlled Prosthetics for Paralysis: Friday Keynote

Formal Analysis Provides Parameters for Guiding Hyperoxidation in Bacteria using Phototoxic Proteins

On the Functions Realized by Stochastic Computing Circuits

Experimental Validation of a Faithful Binary Circuit Model

Dynamic Task Priority Scaling for Thermal Management of Multi-core Processors with Heavy Workload

Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution

Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models

Improving Lifetime of Multicore Soft Real-Time Systems through Global Utilization Control

A Multilayered Design Approach for Efficient Hybrid 3D Photonics Network-on-chip

A Dynamically Reconfigurable RF NoC for Many-Core

Speed Binning Using Machine Learning And On-chip Slack Sensors

Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers

Energy Efficient RRAM Spiking Neural Network for Real Time Classification

Restricted Clustered Neural Network for Storing Real Data

Flip-Mirror-Rotate: An Architecture for Bit-write Reduction and Wear Leveling in Non-volatile Memories

A Ternary Content Addressable Cell Using a Single Phase Change Memory (PCM)

Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line

Design Automation for Biological Models: A Pipeline that Incorporates Spatial and Molecular Complexity

ApproxMA: Approximate Memory Access for Dynamic Precision Scaling

Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model

Reinforcement Learning for Thermal-aware Many-core Task Allocation

DRAM based Intrinsic Physical Unclonable Functions for System Level Security

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization

Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures

Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design

Analyzing the Dark Silicon Phenomenon in a Many-Core Chip Multi-Processor under Deeply-Scaled Process Technologies

Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems

MSCS: Multi-hop Segmented Circuit Switching

On-chip Sparse Learning with Resistive Cross-point Array Architecture

NeuroDSP Accelerator for Face Detection Application

Fine-Grained Voltage Boosting for Improving Yield in Near-Threshold Many-Core Processors

Characterization of SWCNT Bundle Based VLSI Interconnect with Self-heating Induced Scatterings

Inevitability of Phase-locking in a Charge Pump Phase Lock Loop using Deductive Verification

Mammalian Synthetic Gene Networks

A Comparative Review and Evaluation of Approximate Adders

A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling

Revisiting Dynamic Thermal Management Exploiting Inverse Thermal Dependence

An Effective TSV Self-Repair Scheme for 3D-Stacked ICs

A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits

A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization

Approximate Multiplier Architectures Through Partial Product Perforation: Power-Area Tradeoffs Analysis

A Novel True Random Number Generator Design Leveraging Emerging Memristor Technology

A Novel Static D-Flip-Flop Topology for Low Swing Clocking

Automation of Biological Model Learning, Design and Analysis

Minimizing Error of Stochastic Computation through Linear Transformation

Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx Memory

Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits

A SystemC Platform for Signal Transduction Modelling and Simulation in Systems Biology

TFET-based Operational Transconductance Amplifier Design for CNN Systems

Voltage-Boosted Synchronizers

Optimizing VMIN of ROM Arrays Without Loss of Noise Margin

Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small $I_{cell}$ SRAM Using FinFET

Yield-aware Performance-Cost Characterization for Multi-Core SIMT

Statistically Validating the Impact of Process Variations on Analog and Mixed Signal Designs

An Efficient Approach to Sample On-Chip Power Supplies

The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short Data

Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding

Reduced-latency LLR-based SC List Decoder for Polar Codes

Dynamic Power Reduction Techniques in On-Chip Photonic Interconnects

Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs

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