NDLI: Reducing cache power with low-cost, multi-bit error-correcting codes

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Reducing cache power with low-cost, multi-bit error-correcting codes

Content Provider	ACM Digital Library
Author	Somasekhar, Dinesh Lu, Shih-lien Chishti, Zeshan Wilkerson, Chris Wu, Wei Alameldeen, Alaa R.
Abstract	Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically refreshed to retain data. Like SRAM, eDRAM is susceptible to device variations, which play a role in determining refresh time for eDRAM cells. Refresh power potentially represents a large fraction of overall system power, particularly during low-power states when the CPU is idle. Future designs need to reduce cache power without incurring the high cost of flushing cache data when entering low-power states. In this paper, we show the significant impact of variations on refresh time and cache power consumption for large eDRAM caches. We propose Hi-ECC, a technique that incorporates multi-bit error-correcting codes to significantly reduce refresh rate. Multi-bit error-correcting codes usually have a complex decoder design and high storage cost. Hi-ECC avoids the decoder complexity by using strong ECC codes to identify and disable sections of the cache with multi-bit failures, while providing efficient single-bit error correction for the common case. Hi-ECC includes additional optimizations that allow us to amortize the storage cost of the code over large data words, providing the benefit of multi-bit correction at same storage cost as a single-bit error-correcting (SECDED) code (2% overhead). Our proposal achieves a 93% reduction in refresh power vs. a baseline eDRAM cache without error correcting capability, and a 66% reduction in refresh power vs. a system using SECDED codes.
Starting Page	83
Ending Page	93
Page Count	11
File Format	PDF
ISBN	9781450300537
DOI	10.1145/1815961.1815973
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-06-19
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Idle power Ecc Edram Dram Multi-bit ecc Refresh power Vccmin Idle states
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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