NDLI: Translation caching: skip, don't walk (the page table)

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Translation caching: skip, don't walk (the page table)

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Translation caching: skip, don't walk (the page table)

Content Provider	ACM Digital Library
Author	Cox, Alan L. Rixner, Scott Barr, Thomas W.
Abstract	This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page table. In particular, these caches accelerate the page table walk that occurs after a miss in the Translation Lookaside Buffer. This paper shows that the most effective MMU caches are translation caches, which store partial translations and allow the page walk hardware to skip one or more levels of the page table. In recent years, both AMD and Intel processors have implemented MMU caches. However, their implementations are quite different and represent distinct points in the design space. This paper introduces three new MMU cache structures that round out the design space and directly compares the effectiveness of all five organizations. This comparison shows that two of the newly introduced structures, both of which are translation cache variants, are better than existing structures in many situations. Finally, this paper contributes to the age-old discourse concerning the relative effectiveness of different page table organizations. Generally speaking, earlier studies concluded that organizations based on hashing, such as the inverted page table, outperformed organizations based upon radix trees for supporting large virtual address spaces. However, these studies did not take into account the possibility of caching page table entries from the higher levels of the radix tree. This paper shows that any of the five MMU cache structures will reduce radix tree page table DRAM accesses far below an inverted page table.
Starting Page	48
Ending Page	59
Page Count	12
File Format	PDF
ISBN	9781450300537
DOI	10.1145/1815961.1815970
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-06-19
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Page walk caching Memory management Tlb
Content Type	Text
Resource Type	Article

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