NDLI: Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing

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Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing

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Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing

Content Provider	ACM Digital Library
Author	Soyata, Tolga Guo, Xiaochen Ipek, Engin
Abstract	As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces an exponential increase in subthreshold leakage. As a result, leakage power has become comparable to dynamic power in current-generation processes, and will soon exceed it in magnitude if voltages are scaled down any further. Beyond this inflection point, multicore processors will not be able to afford keeping more than a small fraction of all cores active at any given moment. Multicore scaling will soon hit a power wall. This paper presents resistive computation, a new technique that aims at avoiding the power wall by migrating most of the functionality of a modern microprocessor from CMOS to spin-torque transfer magnetoresistive RAM (STT-MRAM)---a CMOS-compatible, leakage-resistant, non-volatile resistive memory technology. By implementing much of the on-chip storage and combinational logic using leakage-resistant, scalable RAM blocks and lookup tables, and by carefully re-architecting the pipeline, an STT-MRAM based implementation of an eight-core Sun Niagara-like CMT processor reduces chip-wide power dissipation by 1.7× and leakage power by 2.1× at the 32nm technology node, while maintaining 93% of the system throughput of a CMOS-based design.
Starting Page	371
Ending Page	382
Page Count	12
File Format	PDF
ISBN	9781450300537
DOI	10.1145/1815961.1816012
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-06-19
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Stt-mram Power-efficiency
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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