NDLI: 100x Evolution of Video Codec Chips

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100x Evolution of Video Codec Chips

Content Provider	ACM Digital Library
Author	Zhou, Jinjia Goto, Satoshi Zhou, Dajiang
Abstract	In the past two decades, there has been tremendous progress in video compression technologies. Meanwhile, the use of these technologies, along with the ever-increasing demand for emerging ultra-high-definition applications greatly challenges the design of video codec chips, with the extensive requirements on both memory (DRAM) bandwidth and computation power. Besides, the high data dependencies of video coding algorithms restrict the degree of efficient hardware parallelism and pipelining. This paper describes the techniques to realize high-performance video codec chips. Firstly, we introduce various optimization techniques to solve the DRAM traffic issue. Furthermore, the techniques to reduce the computational complexity and alleviate data dependencies are described. The proposed techniques have been implemented in several ASIC video codecs. Experiments show that the DRAM traffic and DRAM access time are reduced by 80% and 90% respectively. The performance of the video codec chips can achieve 7680x4320@120fps, which is more than 100x better than previous works.
Starting Page	121
Ending Page	122
Page Count	2
File Format	PDF
ISBN	9781450346962
DOI	10.1145/3036669.3038252
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-03-19
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Video coding Memory bandwidth Vlsi Low power Uhdtv
Content Type	Text
Resource Type	Article

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