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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yue Pan Dajiang Zhou Goto, S. |
| Copyright Year | 2013 |
| Description | Author affiliation: Grad. Sch. of Inf., Waseda Univ., Kitakyushu, Japan (Yue Pan; Dajiang Zhou; Goto, S.) |
| Abstract | An FPGA design of 4K UHDTV (Ultra-high definition TV) H.264 video decoder is proposed in this paper. The decoder is a complete one starting from bit stream input to decoding and final displaying, all of which are implemented on FPGA. Decoder engine that saves 51% DRAM bandwidth and display frame buffer addressing scheme that increases DRAM efficiency by 45% are proposed. The proposed work is capable of decoding and displaying a 3840×2160@30fps video in real time by 2 Altera Stratix III EP3SL150 DE3 FPGA boards (video decoding uses only one board) and four 1080p HDMI daughter boards. In this paper, the system structure, the FPGA configuration scheme, and particular designs targeting DRAM access efficiency are described. Besides, main specifications of the design and also the final performance are reported. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 645110 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479916047 |
| DOI | 10.1109/ICMEW.2013.6618319 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-07-15 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Video coding DRAM bandwidth FPGA Random access memory Decoding HDMI displaying H.264/AVC Engines Video decoder 4K UHDTV Bandwidth Streaming media Field programmable gate arrays |
| Content Type | Text |
| Resource Type | Article |
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