| Abstract |
On behalf of the organizing committee, we are delighted to welcome you to the 2017 ACM International Symposium on Physical Design (ISPD), held at Portland-Lake Oswego, Oregon. Continuing the great tradition established by its twenty-five predecessors, which includes a series of five ACM/SIGDA Physical Design Workshops held intermittently in 1987-1996 and twenty editions of ISPD in the current form since 1997, the 2017 ISPD provides a premier forum to present leading-edge research results, exchange ideas, and promote research on critical areas related to the physical design of VLSI and other related systems. The regular papers in the ISPD 2017 program were selected after a rigorous, month-long, doubleblind review process and a face-to-face meeting by the Technical Program Committee (TPC) members. The papers selected exhibit latest advancements in a variety of topics in physical design, including emerging challenges for current and future process technologies, FPGA layout, clock construction and timing analysis, and application of machine-learning based techniques to physical design. The ISPD 2017 program is complemented by three keynote addresses, fourteen invited talks and a tribute session, all of which are delivered by distinguished researchers from both industry and academia. Two of the keynote speeches are on Monday. In the morning, Dr. Ian Young, senior fellow of Intel Corporation, will talk about technology options for beyond CMOS. In the afternoon, Dr. Ivo Bolsens, CTO and senior VP of Xilinx, will talk about the transition from FPGA to the All Programmable Platform. In the third keynote speech on Tuesday, Dr. Lee-Chung Lu, senior director and fellow of TSMC, will present the physical design challenges and innovations to meet the power, speed, and area scaling trends. A commemorative session on Tuesday afternoon will pay tribute to Professor Satoshi Goto. His collaborators will share with us Dr. Goto's exceptional contributions to research in physical design and VLSI applications, including his influential work on placement tools. There will be other invited talks interspersed with the presentations of the regular papers. The topics of the invited papers range from clock construction, physical optimization, machine learning in EDA, security-aware physical design, inmemory computing, and FPGA EDA. Since 2005, the ISPD has organized highly competitive contests to promote and advance research in placement, global routing, clock network synthesis, discrete gate sizing, and detailed routingdriven placement. The contest this year, organized by Xilinx, is on FPGA placement. Different from last year's contest, which was also on FPGA placement, this year's contest focuses on the placement of clocking components. Continuing the tradition of all the past contests, a new largescale real-world benchmark suite for FPGA circuits based on an advanced heterogeneous FPGA architecture will be released in the ISPD website (http://www.ispd.cc). The contest evaluates the quality of an FPGA placement with an advanced commercial FPGA routing tool making the problem even more challenging and practical. It is expected to lead and motivate more research and contributions on FPGA physical design. |
