NDLI: Proceedings of the 2015 Symposium on International Symposium on Physical Design (ISPD '15)

Please wait, while we are loading the content...

3D VLSI: A Scalable Integration Beyond 2D

BonnPlace: A Self-Stabilizing Placement Framework

Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation

Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning

Concept & Research to Revenue: An Entrepreneurial Story

Analog Circuit and Layout Synthesis Revisited

A Useful Skew Tree Framework for Inserting Large Safety Margins

Accelerated Path-Based Timing Analysis with MapReduce

Early Days of Circuit Placement

Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression

FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology

Coarse-grained Structural Placement for a Synthesized Parallel Multiplier

SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips

A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography

Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging

Blech Effect in Interconnects: Applications and Design Guidelines

Force-Directed Placement of VLSI Circuits

Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability

Open Cell Library in 15nm FreePDK Technology

Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment

Machine Learning in Simulation-Based Analysis

TPL-Aware Displacement-driven Detailed Placement Refinement with Coloring Constraints

Physical Design Challenges in the Chip Power Distribution Network

On Resilient System Performance Binning

Beyond GORDIAN and Kraftwerk: EDA Research at TUM

ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement

Design Rule Management and its Applications in 15nm FreePDK Technology

Automation of Analog IC Layout: Challenges and Solutions

From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges

A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design

Proceedings of the 2015 Symposium on International Symposium on Physical Design (ISPD '15)

Content Provider	ACM Digital Library
Editor	Chinnery, David Davoodi, Azadeh Mo, Yuyen Hill, Dwight Cao, Aiqun Chen, Hung-Ming Yan, Jackey Kahng, Andrew Groeneveld, Patrick Menezes, Noel Young, Evangeline Zhang, Hongbo
Copyright Year	2015
Abstract	On behalf of the organizing committee, we are delighted to welcome you to the 2015 ACM International Symposium on Physical Design (ISPD), held at Monterey, California. Continuing the great tradition established by its twenty-three predecessors, which includes a series of five ACM/SIGDA Physical Design Workshops held intermittently in 1987-1996 and eighteen editions of ISPD in the current form since 1997, the 2015 ISPD provides a premier forum to present leadingedge research results, exchange ideas, and promote research on critical areas related to the physical design of VLSI and other related systems. We received 44 abstract submissions and 37 full submissions from all around the world. After a rigorous, month-long, double-blind review process, the Technical Program Committee (TPC) met face-to-face to select papers to be included in the technical program based on 185 reviews provided by 18 TPC members and 39 external reviewers. Finally, the committee accepted 14 papers to be presented in the symposium. These papers exhibit latest advancements in a variety of topics in placement, routing, 3D integration, clocking, power network planning, design for manufacturability, and physical design with latest machine learning approaches. The ISPD 2015 program is complemented by two keynote addresses, seven invited talks and an invited session on FreePDK library, all of which are delivered by distinguished researchers in both industry and academia. Dr. Karim Arabi, Vice President, Engineering at Qualcomm will present in the Monday keynote speech, challenges and opportunities in scalable integration of 3D VLSI. Dr. Rob Rutenbar, Abel Bliss Professor and Head of the Department of Computer Science in the University of Illinois at Urbana-Champaign will present in the Tuesday keynote speech on analog circuit and layout synthesis. A commemorative session on Tuesday afternoon pays a tribute to Dr. Kurt Antreich. His collaborators will share with us Dr. Antreich's exceptional contributions to EDA research, including his pioneering effort in analytical circuit placement, which still has significant impact on various placement methods today. The other invited talks will be interspersed with the presentations of accepted papers. The topics of the invited papers range from emerging technologies like directed self-assembly circuits, monolithic 3D ICs, to modern challenges in analog IC layout and applications of machine learning in physical design. Since 2005, ISPD has organized highly competitive contests to promote and advance research in placement, global routing, clock network synthesis, and discrete gate sizing. This year's contest is on detailed routing-driven placement and is organized by Mentor Graphics. Specifically, this is the second year of this topic and the problem is made even more challenging by imposing constraints of fence regions and placement blockages, besides the detailed pin, cell and wire geometry constraints in 2014. The contest evaluates the quality of a placement with a commercial detailed router in order to motivate research to address significant complexity of routing-design rules in sub-20nm nodes. Continuing the tradition of all the past contests, a new large-scale real-world benchmark suite will be released in industry-standard formats including LEF, DEF, and Verilog description in the ISPD website: http://www.ispd.cc.
ISBN	9781450333993
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-03-29
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in