NDLI: Traversal caches: a first step towards FPGA acceleration of pointer-based data structures

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Traversal caches: a first step towards FPGA acceleration of pointer-based data structures

Content Provider	ACM Digital Library
Author	Stitt, Greg Chaudhari, Gaurav Coole, James
Abstract	Field-programmable gate arrays (FPGAs) often achieve order of magnitude speedups compared to microprocessors, but typically have been unable to improve the performance of applications with irregular memory access patterns, such as traversals of pointer-based data structures. Due to the common use of these data structures, the applicability and widespread success of FPGAs has been limited. In this paper, we introduce the traversal cache framework - a first step towards improving the performance of FPGA applications that utilize pointer-based data structures. The traversal cache is a local FPGA memory that stores repeated traversals of pointer-based data structures, allowing for these traversals to be efficiently streamed into the FPGA. Although the cache is generally limited to improving applications that exhibit repeated traversals, we show that many applications in fact have this characteristic. Furthermore, we show that few repetitions are needed to achieve performance improvements. We present experimental results showing that FPGA implementations using the traversal cache framework achieve speedups ranging from 7x to 29x compared to pointer-based software on a 3.2 GHz Xeon.
Starting Page	61
Ending Page	66
Page Count	6
File Format	PDF
ISBN	9781605584706
DOI	10.1145/1450135.1450150
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-10-19
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Synthesis Pointers Fpga Traversal cache Hardware/software partitioning Cad
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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