NDLI: Distributed and low-power synchronization architecture for embedded multiprocessors

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Distributed and low-power synchronization architecture for embedded multiprocessors

Content Provider	ACM Digital Library
Author	Petrov, Peter Yu, Chenjie
Abstract	In this paper we present a framework for a distributed and very low-cost implementation of synchronization controllers and protocols for embedded multiprocessors. The proposed architecture effectively implements the queued-lock semantics in a completely distributed way. The proposed approach to synchronization implementation not only completely eliminates the overwhelming bus contention traffic when multiple cores compete for a synchronization variable, but also achieves very high energy efficiency as the local synchronization controller can efficiently determine, without any bus transactions or local cache spinning, the exact timing of when the lock is made available to the local processor. Application-specific information regarding synchronization variables in the local task is exploited in implementing the distributed synchronization protocol. The local synchronization controllers enable the system software or the thread library to implement various low-power policies, such as disabling the cache accesses or even completely powering down the local processor while waiting for a synchronization variable.
Starting Page	73
Ending Page	78
Page Count	6
File Format	PDF
ISBN	9781605584706
DOI	10.1145/1450135.1450153
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-10-19
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Multiprocessor Synchronization
Content Type	Text
Resource Type	Article

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