NDLI: FPGA-based Data Partitioning

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FPGA-based Data Partitioning

Content Provider	ACM Digital Library
Author	Kara, Kaan Giceva, Jana Alonso, Gustavo
Abstract	Implementing parallel operators in multi-core machines often involves a data partitioning step that divides the data into cache-size blocks and arranges them so to allow concurrent threads to process them in parallel. Data partitioning is expensive, in some cases up to 90% of the cost of, e.g., a parallel hash join. In this paper we explore the use of an FPGA to accelerate data partitioning. We do so in the context of new hybrid architectures where the FPGA is located as a co-processor residing on a socket and with coherent access to the same memory as the CPU residing on the other socket. Such an architecture reduces data transfer overheads between the CPU and the FPGA, enabling hybrid operator execution where the partitioning happens on the FPGA and the build and probe phases of a join happen on the CPU. Our experiments demonstrate that FPGA-based partitioning is significantly faster and more robust than CPU-based partitioning. The results open interesting options as FPGAs are gradually integrated tighter with the CPU.
Starting Page	433
Ending Page	445
Page Count	13
File Format	PDF
ISBN	9781450341974
DOI	10.1145/3035918.3035946
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-05-09
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Data partitioning Fpga Hash join Hardware acceleration
Content Type	Text
Resource Type	Article

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