NDLI: Timing-driven placement for hierarchical programmable logic devices

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Timing-driven placement for hierarchical programmable logic devices

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Timing-driven placement for hierarchical programmable logic devices

Content Provider	ACM Digital Library
Author	Hutton, Michael Leaver, Andrew Adibsamii, Khosrow
Abstract	In this paper we discuss new techniques for timing-driven placement and adaptive delay computation for hierarchical PLD architectures.Our algorithm follows the natural recursive k-way partitioning-based approach to placement on such devices. Our contributions include a specification of the overall TDC (timing-driven compilation) algorithm, an analysis of heuristics such as a variant of multi-start partitioning, a new method for adaptive delay computation, and a discussion of the structure of critical paths and sub-graphs on modern PLD designs.This algorithm has been implemented in a production quality commercial tool, and we report on the results with and without the implementation of the new techniques. The basic result is a substantial 38.5% average (36.3% median) improvement in register-to-register performance across a range of real designs in modern density ranges, at a cost of approximately 3.65X average (2.88X median) place-and-route CPU time. (These improvements and costs are relative to the same tool prior to the efforts described in this paper.) A partial implementation of the new algorithm shows approximately half the performance gain, with approximately half the compile time cost.
Starting Page	3
Ending Page	11
Page Count	9
File Format	PDF
ISBN	1581133413
DOI	10.1145/360276.360286
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2001-02-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Partitioning Cpld Fpga Heuristic algorithm Placement Timing-driven placement Programmable logic Algorithm
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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