NDLI: Improved practical differential fault analysis of grain-128

Please wait, while we are loading the content...

Clock domain crossing aware sequential clock gating

Online binding of applications to multiple clock domains in shared FPGA-based systems

Workload uncertainty characterization and adaptive frequency scaling for energy minimization of embedded systems

Automatic extraction of assertions from execution traces of behavioural models

Low-cost checkpointing in automotive safety-relevant systems

Joint affine transformation and loop pipelining for mapping nested loop on CGRAs

Reliable information extraction for single trace attacks

Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis

SelectDirectory: a selective directory for cache coherence in many-core architectures

Variation-aware evaluation of MPSoC task allocation and scheduling strategies using statistical model checking

Delay analysis of structural real-time workload

Error recovery in digital microfluidics for personalized medicine

High-resolution online power monitoring for modern microprocessors

Privacy-preserving functional IP verification utilizing fully homomorphic encryption

An online thermal-constrained task scheduler for 3D multi-core processors

Soft-error reliability and power co-optimization for GPGPUS register file using resistive memory

Systematic application of ISO 26262 on a SEooC: Support by applying a systematic reuse approach

A defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systems

Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI

Improved practical differential fault analysis of grain-128

Exploiting DRAM restore time variations in deep sub-micron scaling

Coherent crosstalk noise analyses in ring-based optical interconnects

Sufficient response time analysis considering dependencies between rate-dependent tasks

On the statistical memory architecture exploration and optimization

Optimized selection of reliable and cost-effective cyber-physical system architectures

Comparison of multi-purpose cores of Keccak and AES

The human intranet: where swarms and humans meet

Efficient attacks on robust ring oscillator PUF with enhanced challenge-response set

Asymmetric underlapped FinFET based robust SRAM design at 7nm node

A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters

DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS

Adaptive on-the-fly application performance modeling for many cores

Computing approximately, and efficiently

Introduction to hardware trojan detection methods

Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting

Axilog: language support for approximate hardware design

DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip

STT MRAM-Based PUFs

HLC: software-based half-level-cell flash memory

A thermal stress-aware algorithm for power and temperature management of MPSoCs

DSP based programmable FHD HEVC decoder

Spintronic devices as key elements for energy-efficient neuroinspired architectures

Efficient bit error rate estimation for high-speed link by Bayesian model fusion

Bytecode-to-C ahead-of-time compilation for Android Dalvik virtual machine

Transparent acceleration of program execution using reconfigurable hardware

PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation

Optimization of quantum computer architecture using a resource-performance simulator

Dynamic power and performance back-annotation for fast and accurate functional hardware simulation

Knowledge-intensive, causal reasoning for analog circuit topology synthesis in emergent and innovative applications

Quick error detection tests with fast runtimes for effective post-silicon validation and debug

A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool

PWL: a progressive wear leveling to minimize data migration overheads for nand flash devices

Gait analysis for fall prediction using hierarchical textile-based capacitive sensor arrays

HReRAM: a hybrid reconfigurable resistive random-access memory

The federated scheduling of constrained-deadline sporadic DAG task systems

Memory fast-forward: a low cost special function unit to enhance energy efficiency in GPU for big data processing

Hybrid adaptive clock management for FPGA processor acceleration

Fast eye diagram analysis for high-speed CMOS circuits

Automated rectification methodologies to functional state-space unreachability

Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model

A new approximate adder with low relative error and correct sign calculation

Paper, pen and ink: an innovative system and software framework to assist writing rehabilitation

SAPPHIRE: an always-on context-aware computer vision system for portable devices

MatEx: efficient transient and peak temperature computation for compact thermal models

Towards systematic design of 3D pNML layouts

An ultra-low power dual-mode ECG monitor for healthcare and wellness

Solving DQBF through quantifier elimination

An effective triple patterning aware grid-based detailed routing approach

Models for deterministic execution of real-time multiprocessor applications

Tackling the bottleneck of delay tables in 3D ultrasound imaging

The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems

Multi/many-core programming: where are we standing?

Memristor based computation-in-memory architecture for data-intensive applications

The future of electronics, semiconductors, and design in Europe: panel

An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes

Profiling-driven multi-cycling in FPGA high-level synthesis

Formal analysis of the startup delay of SOME/IP service discovery

A methodology for automated design of embedded bit-flips detectors in post-silicon validation

Uncertainty-aware reliability analysis and optimization

Path selection based acceleration of conditionals in CGRAs

Scandalee: a side-channel-based disassembler using local electromagnetic emanations

Interplay of loop unrolling and multidimensional memory partitioning in HLS

DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes

A fast parallel sparse solver for SPICE-based circuit simulators

Effective verification of low-level software with nested interrupts

A cyber-physical systems approach to personalized medicine: challenges and opportunities for noc-based multicore platforms

Reducing energy consumption in microcontroller-based platforms with low design margin co-processors

Efficient software implementation of ring-LWE encryption

A symbolic system synthesis approach for hard real-time systems based on coordinated SMT-solving

Energy-efficient cache design in emerging mobile platforms: the implications and optimizations

Timing analysis of an avionics case study on complex hardware/software platforms

Temperature-aware software-based self-testing for delay faults

Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell

A score-based classification method for identifying hardware-trojans at gate-level netlists

Adaptively tolerate power-gating-induced power/ground noise under process variations

Enabling vertical wormhole switching in 3D NoC-bus hybrid systems

Engine control: task modeling and analysis

ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell

Software assisted non-volatile register reduction for energy harvesting based cyber-physical system

On-line prediction of NBTI-induced aging rates

A robust authentication methodology using physically unclonable functions in DRAM arrays

Quality configurable reduce-and-rank for energy efficient approximate computing

Eliminating intra-warp conflict misses in GPU

A small non-volatile write buffer to reduce storage writes in smartphones

Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints

Novel inexact memory aware algorithm co-design for energy efficient computation: algorithmic principles

New testing procedure for finding insertion sites of stealthy hardware trojans

$d^{2}-LBDR:$ distance-driven routing to handle permanent failures in 2D mesh NOCs

Improving MPSoC reliability through adapting runtime task schedule based on time-correlated fault behavior

A scan partitioning algorithm for reducing capture power of delay-fault LBIST

Spiking neural network with RRAM: can we use it for real-world application?

Spatial and temporal granularity limits of body biasing in UTBB-FDSOI

AHEAD: automated framework for hardware accelerated iterative data analysis

Predictive dynamic thermal and power management for heterogeneous mobile platforms

Accelerating complex brain-model simulations on GPU platforms

Giant spin hall effect (GSHE) logic design for low power application

Fast deployment of alternate analog test using Bayesian model fusion

A basic linear algebra compiler for embedded processors

Accelerating arithmetic kernels with coherent attached FPGA coprocessors

Rate-based vs delay-based control for DVFS in NoC

Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers

Fast and precise cache performance estimation for out-of-order execution

A CNN-inspired mixed signal processor based on tunnel transistors

GPU-accelerated small delay fault simulation

Monolithic 3D integration: a path from concept to reality

Towards trustable storage using SSDs with proprietary FTL

nCode: limiting harmful writes to emerging mobile NVRAM through code swapping

Run and be safe: mixed-criticality scheduling with temporary processor speedup

Power minimization for data center with guaranteed QoS

A scalable and high-density FPGA architecture with multi-level phase change memory

Statistical library characterization using belief propagation across multiple technology nodes

Over-approximating loops to prove properties using bounded model checking

Impact of process-variations in STTRAM and adaptive boosting for robustness

Towards binary circuit models that faithfully capture physical solvability

An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission

Approximate associative memristive memory for energy-efficient GPUs

Distributed reinforcement learning for power limited many-core system performance optimization

DESTINY: a tool for modeling emerging 3D NVM and eDRAM caches

Formal verification of sequential Galois field arithmetic circuits using algebraic geometry

Simultaneous transistor pairing and placement for CMOS standard cells

Pre-simulation symbolic analysis of synchronization issues between discrete event and timed data flow models of computation

Integrated CMOS receiver for wearable coil arrays in MRI applications

Race to idle or not: balancing the memory sleep time with DVS for energy minimization

Schedulability bound for integrated modular avionics partitions

Analysis of ethernet-switch traffic shapers for in-vehicle networking applications

Data mining diagnostics and bug MRIs for HW bug localization

Efficient soft error vulnerability estimation of complex designs

Hardware-assisted code obfuscation for FPGA soft microprocessors

Side-channel attacks from static power: when should we care?

Inter-tile reuse optimization applied to bandwidth constrained embedded accelerators

Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache

MRP: mix real cores and pseudo cores for FPGA-based chip-multiprocessor simulation

Platform-specific timing verification framework in model-based implementation

On-chip network-enabled many-core architectures for computational biology applications

De-elastisation: from asynchronous dataflows to synchronous circuits

Embedded HW/SW platform for on-the-fly testing of true random number generators

E-pipeline: elastic hardware/software pipelines on a many-core fabric

Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment

Silicon proof of the intelligent analog IP design flow for flexible automotive components

Operational fault detection and monitoring of a memristor-based LUT

Fault modeling in controllable polarity silicon nanowire circuits

Hardware trojan detection for gate-level ICs using signal correlation based clustering

Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories

A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures

Evaluation of diverse compiling for software-fault detection

Subpage programming for extending the lifetime of NAND flash memory

A re-entrant flowshop heuristic for online scheduling of the paper path in a large scale printer

Retraining-based timing error mitigation for hardware neural networks

A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics

Ultra-low-power ECG front-end design based on compressed sensing

RNA: a reconfigurable architecture for hardware neural acceleration

Clustering-based multi-touch algorithm framework for the tracking problem with a large number of points

Enabling multi-threaded applications on hybrid shared memory manycore architectures

Designing inexact systems efficiently using elimination heuristics

Hardware trojan detection by delay and electromagnetic measurements

Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration

ACSEM: accuracy-configurable fast soft error masking analysis in combinatorial circuits

Architecture of ring-based redundant TSV for clustered faults

Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology

A hardware implementation of a radial basis function neural network using stochastic logic

Design method for multiplier-less two-variable numeric function approximation

Power-efficient control of thermoelectric coolers considering distributed hot spots

A packet-switched interconnect for many-core systems with BE and RT service

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm

Bordersearch: an adaptive identification of failure regions

VARSHA: variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era

Transparent offloading of computational hotspots from binary code to Xeon Phi

NoC-enabled multicore architectures for stochastic analysis of biomolecular reactions

Thermal aware design method for VCSEL-based on-chip optical interconnect

A calibration based thermal modeling technique for complex multicore systems

Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction

Fault simulation with parallel exact critical path tracing in multiple core environment

A ultra-low-power FPGA based on monolithically integrated RRAMs

User-specific skin temperature-aware DVFS for smartphones

System level exploration of a STT-MRAM based level 1 data-cache

Multi-core fixed-priority scheduling of real-time tasks with statistical deadline guarantee

Energy-aware cooling for hot-water cooled supercomputers

FPGA accelerated DNA error correction

Combining adaptive alternate test and multi-site

Automatic extraction of micro-architectural models of communication fabrics from register transfer level designs

Device/circuit/architecture co-design of reliable STT-MRAM

A coupling area reduction technique applying ODC shifting

A pulsed-index technique for single-channel, low-power, dynamic signaling

Platform-aware dynamic configuration support for efficient text processing on heterogeneous system

An energy-efficient virtual channel power-gating mechanism for on-chip networks

Big-data streaming applications scheduling with online learning and concept drift detection

A universal macro block mapping scheme for arithmetic circuits

A TSV noise-aware 3-D placer

Formal consistency checking over specifications in natural languages

Tactile prosthetics in WiseSkin

Event-driven and sensorless photovoltaic system reconfiguration for electric vehicles

Real-time capable CAN to AVB ethernet gateway using frame aggregation and scheduling

RTL property abstraction for TLM assertion-based verification

Detection of illegitimate access to JTAG via statistical learning in chip

Extrax: security extension to extract cache resident information for snoop-based external monitors

A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems

Source level performance simulation of GPU cores

Architecture description language based retargetable symbolic execution

Automated feature localization for dynamically generated SystemC designs

Variability-aware dark silicon management in on-chip many-core systems

Fast optical simulation from a reduced set of impulse responses using SystemC-AMS

Power-aware online testing of manycore systems in the dark silicon era

Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs

Worst-case communication time analysis of networks-on-chip with shared virtual channels

MPIOV: scaling hardware-based I/O virtualization for mixed-criticality embedded real-time systems using non transparent bridges to (multi-core) multi-processor systems

Dictionary-based sparse representation for resolution improvement in laser voltage imaging of CMOS integrated circuits

GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games

ApproxANN: an approximate computing framework for artificial neural network

A low energy 2D adaptive median filter hardware

Opportunities for energy efficient computing: a study of inexact general purpose processors for high-performance and big-data applications

A high efficiency hardware trojan detection technique based on fast SEM imaging

Energy minimization for fault tolerant scheduling of periodic fixed-priority applications on multiprocessor platforms

SODA: software defined FPGA based accelerators for big data

Reducing trace size in multimedia applications endurance tests

Potential applications based on NVM emerging technologies

A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits

Transparent linking of compiled software and synthesized hardware

Initial transient response of oscillators with long settling time

On the automatic generation of SBST test programs for in-field test

Formal probabilistic analysis of distributed dynamic thermal management

High performance AXI-4.0 based interconnect for extensible smart memory cubes

A method for the estimation of defect detection probability of analog/RF defect-oriented tests

GALS synthesis and verification for xMAS models

Sub-10 nm FinFETs and Tunnel-FETs: from devices to systems

A general design of stochastic circuit and its synthesis

A deblocking filter hardware architecture for the high efficiency video coding standard

M-DTM: migration-based dynamic thermal management for heterogeneous mobile multi-core processors

Design flow and run-time management for compressed FPGA configurations

Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking

Identifying redundant inter-cell margins and its application to reducing routing congestion

Inductor optimization for active cell balancing using geometric programming

Designer-level verification: an industrial experience story

Fault-based attacks on the Bel-T block cipher family

Dynamic reconfigurable puncturing for secure wireless communication

Exploration and design of embedded systems including neural algorithms

From device to system: cross-layer design exploration of racetrack memory

A hybrid Quasi Monte Carlo method for yield aware analog circuit sizing tool

Empirical modelling of FDSOI CMOS inverter for signal/power integrity simulation

Lightweight authentication for secure automotive networks

Minimum current consumption transition time optimization methodology for low power CTS

On the premises and prospects of timing speculation

QR-decomposition architecture based on two-variable numeric function approximation

A new distributed framework for integration of district energy data from heterogeneous devices

Feature selection for alternate test using wrappers: application to an RF LNA case study

On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC

Minimizing the number of process corner simulations during design verification

Impact of interconnect multiple-patterning variability on SRAMs

In-place memory mapping approach for optimized parallel hardware interleaver architectures

Improving SIMD code generation in QEMU

Logical equivalence checking of asynchronous circuits using commercial tools

An approximate voting scheme for reliable computing

Coherence based message prediction for optically interconnected chip multiprocessors

Maximizing common idle time on multi-core processors with shared memory

Reuse distance analysis for locality optimization in loop-dominated applications

May-happen-in-parallel analysis of ESL models using UPPAAL model checking

FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC design

OpenMP and timing predictability: a possible union?

Maximizing IO performance via conflict reduction for flash memory storage systems

TAPP: temperature-aware application mapping for NoC-based many-core processors

Verifying synchronous reactive systems using lazy abstraction

A unified hardware/software MPSoC system construction and run-time framework

SAHARA: a security-aware hazard and risk analysis method

A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors

Malleable NoC: dark silicon inspired adaptable Network-on-Chip

Spintastic: spin-based stochastic logic for energy-efficient computing

$(AS)^{2}:$ accelerator synthesis using algorithmic skeletons for rapid design space exploration

Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation

Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores

Topology identification for smart cells in modular batteries

Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique

Assisted generation of frame conditions for formal models

Occupancy detection via iBeacon on Android devices for smart building management

Power-efficient accelerator allocation in adaptive dark silicon many-core systems

LVS check for photonic integrated circuits: curvilinear feature extraction and validation

SubHunter: a high-performance and scalable sub-circuit recognition method with Prüfer-encoding

Towards a meta-language for the concurrency concern in DSLs

A neural machine interface architecture for real-time artificial lower limb control

Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems

FP-scheduling for mode-controlled dataflow: a case study

Timing verification for adaptive integrated circuits

Fast and accurate branch predictor simulation

Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects

Ageing simulation of analogue circuits and systems using adaptive transient evaluation

A robust approach for process variation aware mask optimization

Comparative study of test generation methods for simulation accelerators

Analog neuromorphic computing enabled by multi-gate programmable resistive devices

A tool for the assisted design of charge redistribution SAR ADCs

FastTree: a hardware KD-tree construction acceleration engine for real-time ray tracing

Using structural relations for checking combinationality of cyclic circuits

An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition

Detection of asymmetric aging-critical voltage conditions in analog power-down mode

Reverse longstaff-schwartz american option pricing on hybrid CPU/FPGA systems

NFRs early estimation through software metrics

High performance single supply CMOS inverter level up shifter for multi: supply voltages domains

Accurate electrothermal modeling of thermoelectric generators

Exploring the impact of functional test programs re-used for power-aware testing

Efficiency-driven design time optimization of a hybrid energy storage system with networked charge transfer interconnect

A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC

Fault diagnosis in designs with extreme low pin test data compressors

Optimizing dynamic trace signal selection using machine learning and linear programming

Improved practical differential fault analysis of grain-128

Content Provider	ACM Digital Library
Author	Dey, Prakash Chakraborty, Abhishek Adhikari, Avishek Mukhopadhyay, Debdeep
Abstract	Differential Fault Attacks (DFA) on stream ciphers have been an active field of research. However, their practical realizations have not been reported in the public literature. Hence, the assumptions on the fault models made in the context of DFA for stream ciphers have not been studied. Furthermore, there have been few efforts reported on the popular stream cipher candidate, Grain-128. We consider a simple low-cost fault injection set-up, using clock glitches and show that in stream ciphers the critical path of the circuit affects few bit positions (the feedback bit for the Shift Registers in the stream ciphers). Thus the fault is often localized to single bit position, and because of the absence of required faulty ciphers makes existing theoretical DFAs invalid. In order to create multiple instance of faults, we use clock glitches to induce the fault, and then use the shifting property of the internal registers of Grain to create multiple instances of contiguously located faults. In parallel, we also develop a more relaxed DFA for Grain-128, to show that when the fault is k neighbourhood bits, k ε {1,.,5}, the attack is successful to retrieve the key without knowing the locations or exact number of bits flipped by the internal fault. We also devise a technique for rejecting the bad faults with high probabilities, i.e., when the faults are not in the contiguous location as required in the attack. Combining the above attacks we demonstrate using a simple set-up via clock glitches that such faults can be practically obtained and analysed using the proposed attack algorithm to retrieve the key.
Starting Page	459
Ending Page	464
Page Count	6
File Format	PDF
ISBN	9783981537048
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-03-09
Publisher Place	San Jose
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in