NDLI: A case for lifetime-aware task mapping in embedded chip multiprocessors

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A case for lifetime-aware task mapping in embedded chip multiprocessors

Content Provider	ACM Digital Library
Author	Thomas, Donald E. Hartman, Adam S. Meyer, Brett H.
Abstract	Temperature-aware design is emerging as a popular approach to addressing a variety of challenges, including system lifetime. In the case of task mapping, temperature-aware approaches indeed improve lifetime due to lifetime's strong dependence on tempera-ture. However, temperature-aware design neglects several impor-tant factors that also influence lifetime: (a) physical parameters such as supply voltage and current density, as well as (b) application and architecture characteristics that affect what failures are survivable. Only lifetime-aware task mapping can expose the relationship between physical parameters, component failure, and system lifetime, and therefore find lifetime-optimal mappings. To address this need, we have developed a new lifetime-aware task mapping technique based on ant colony optimization (ACO). Our technique produces task mappings resulting in lifetimes within 17.9% of the observed optimal results on average, outperforming a lifetime-agnostic task mapping approach by an average of 32.3%. We also observed that the lifetimes resulting from task mappings within 1% of the best maximum system temperature vary by an average of 20.1% while the lifetimes resulting from task mappings within 1% of the best average system temperature vary by an average of 32.6%. Our observations lead us to conclude that one cannot depend on temperature-aware task mapping when system lifetime is a design constraint, but one may depend on lifetime-aware task mapping when one or both of lifetime and temperature are design constraints.
Starting Page	145
Ending Page	154
Page Count	10
File Format	PDF
ISBN	9781605589053
DOI	10.1145/1878961.1878987
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-10-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Ant colony optimization Temperature-aware Lifetime-aware Task mapping
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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