NDLI: Demand-based block-level address mapping in large-scale NAND flash storage systems

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Demand-based block-level address mapping in large-scale NAND flash storage systems

Content Provider	ACM Digital Library
Author	Qin, Zhiwei Shao, Zili Liu, Duo Wang, Yi
Abstract	The increasing capacity of NAND flash memory leads to large RAM footprint on address mapping in the Flash Translation Layer (FTL) design. This paper proposes a novel Demand-based block-level Address mapping scheme with two-level Caching mechanism (DAC) for large-scale NAND flash storage systems. The objective is to reduce RAM footprint without sacrificing too much system response time. In our technique, the block-level address mapping table is stored in fixed pages (called translation pages) in the flash memory. Considering temporal locality that workloads exhibit, we maintain one cache in RAM to store the on-demand block-level address mapping information. Meanwhile, by exploring both spatial locality and access frequency of workloads with another two caches, the second-level cache is designed to cache selected translation pages into RAM. In such a way, address mapping information for both sequential accesses and most-frequently-accessed translation pages can be found in the cache, and therefore, the system response time can be improved. We conduct experiments on a mixture of real-world and synthetic traces. The experimental results show that our technique can significantly reduce the RAM footprint while the average response time is kept well under control. Moreover, our technique shows big improvement on wear-leveling compared with the previous work.
Starting Page	173
Ending Page	182
Page Count	10
File Format	PDF
ISBN	9781605589053
DOI	10.1145/1878961.1878991
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-10-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Nand flash Two-level cache Block-level mapping
Content Type	Text
Resource Type	Article

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