NDLI: A holistic approach to network-on-chip synthesis

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A holistic approach to network-on-chip synthesis

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A holistic approach to network-on-chip synthesis

Content Provider	ACM Digital Library
Author	Chatha, Karam S. Leary, Glenn
Abstract	Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor System-on-Chip architectures. Synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints.
Starting Page	213
Ending Page	222
Page Count	10
File Format	PDF
ISBN	9781605589053
DOI	10.1145/1878961.1879001
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-10-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Multiple use-cases Port arity Deadlock avoidance Synthesis Network-on-chip Best effort
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A holistic approach to Network-on-Chip synthesis

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks

Comparison of deadlock recovery and avoidance mechanisms to approach message dependent deadlocks

Centralized end-to-end flow control in a best-effort network-on-chip

A Lightweight Fault-Tolerant Mechanism for Network-on-Chip

Guaranteed throughput and best effort streams in a network on chip model.

A Unified Approach to Mapping and Routing in a Combined Guaranteed Service and Best-Effort Network-on-Chip Architecture

Automated technique for design of NoC with minimal communication latency

Performance Analysis of Guaranteed Throughput and Best Effort Traffic in Network-on-Chip under Different Traffic Scenario

A holistic approach to network-on-chip synthesis

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