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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chia-An Lin Hsien-Kai Hsin En-Jui Chang Wu, A.-Y.A. |
| Copyright Year | 2013 |
| Description | Author affiliation: Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Chia-An Lin; Hsien-Kai Hsin; En-Jui Chang; Wu, A.-Y.A.) |
| Abstract | With the shrinking size of circuits and the scaling of Network-on-Chip (NoC), the on-chip components will have a higher chance to fail. The on-chip failures can cause traffic congestion and even system crash. To overcome this problem, the NoC routing algorithm should be implemented with fault-tolerant capability. Inspired by the fault-tolerant behavior of ant colony consisting of three steps: Encounter, Search, and Select, we propose Ant Colony Optimization-based Fault-aware Routing (ACO-FAR) algorithm for traffic balancing. To effectively forward the packets to a non-faulty region, three mechanisms of ACO-FAR correspond to the three-step behaviors of ants are proposed in this work. The simulation results show that proposed ACO-FAR has higher throughput than related works by 12.5%-77.7%. Also, this routing method improves the reachable packet ratio to 99.50%-99.98% and the distribution of traffic load in the faulty network. |
| Starting Page | 342 |
| Ending Page | 347 |
| File Size | 1442035 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467362382 |
| ISSN | 21623562 |
| DOI | 10.1109/SiPS.2013.6674530 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-10-16 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Fault-aware Mechanism Ant Colony Optimization Network-on-Chip Fault-tolerant Routing |
| Content Type | Text |
| Resource Type | Article |
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