NDLI: NeuroNoC: neural network inspired runtime adaptation for an on-chip communication architecture

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NeuroNoC: neural network inspired runtime adaptation for an on-chip communication architecture

Content Provider	ACM Digital Library
Author	Ebi, Thomas Henkel, Jörg Al Faruque, Mohammad Abdullah
Abstract	The on-chip communication architecture presented in this paper, NeuroNoC, addresses the problems arising in large multi-core systems where global or local routing strategies do not work efficiently anymore since they either do not scale or lack information on the network state. Our communication architecture is runtime adaptive and it deploys a distributed artificial neural network to aid routing decisions. It thereby provides a light-weight mechanism for local routing information to propagate through the communication architecture and is capable of self-organizing efficiently (since scalable) to varying communication workload scenarios. The underlying basic concepts are borrowed from spiking neural networks, a special case of artificial neural networks. Our experiments show that already with low hardware overhead, a significant improvement of the runtime routing behavior compared to current state-of-the-art approaches is possible. We report an improvement of 23% in routing quality compared to wXY [9] routing in terms of failed transactions.
Starting Page	223
Ending Page	230
Page Count	8
File Format	PDF
ISBN	9781605589053
DOI	10.1145/1878961.1879002
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-10-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Adaptive system Network-on-chip Spiking neural networks
Content Type	Text
Resource Type	Article

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