NDLI: Staged memory scheduling:achieving high performance and scalability in heterogeneous systems

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Volume 40, Issue 5, December 2012

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Simultaneous branch and warp interweaving for sustained GPU performance

Branch regulation

Tolerating process variations in nanophotonic on-chip networks

Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)

Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures

Reducing memory reference energy with opportunistic virtual caching

Setting an error detection infrastructure with low cost acoustic wave detectors

A case for exploiting subarray-level parallelism (SALP) in DRAM

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Can traditional programming bridge the Ninja performance gap for parallel computing applications?

Configurable fine-grain protection for multicore processor virtualization

Managing distributed ups energy for effective power capping in data centers

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A micro-architectural analysis of switched photonic multi-chip interconnects

The yin and yang of power and performance for asymmetric hardware and managed software

A first-order mechanistic model for architectural vulnerability factor

Improving writeback efficiency with decoupled last-write prediction

Staged memory scheduling

Revisiting hardware-assisted page walks for virtualized systems

Scale-out processors

Enhancing effective throughput for transmission line-based bus

A defect-tolerant accelerator for emerging high-performance applications

Buffer-on-board memory systems

Probabilistic shared cache management (PriSM)

The dynamic granularity memory system

Towards energy-proportional datacenter memory with mobile DRAM

Boosting mobile GPU performance with a decoupled access/execute fragment processor

Inspection resistant memory

A case for random shortcut topologies for HPC interconnects

Volume 40, Issue 2, May 2012

Volume 40, Issue 1, March 2012

Staged memory scheduling:achieving high performance and scalability in heterogeneous systems

Content Provider	ACM Digital Library
Author	Subramanian, Lavanya Chang, Kevin Kai-Wei Loh, Gabriel H. Mutlu, Onur Ausavarungnirun, Rachata
Abstract	When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from the CPU cores, leading to low system performance and starvation of CPU cores. Unfortunately, state-of-the-art application-aware memory scheduling algorithms are ineffective at solving this problem at low complexity due to the large amount of GPU traffic. A large and costly request buffer is needed to provide these algorithms with enough visibility across the global request stream, requiring relatively complex hardware implementations. This paper proposes a fundamentally new approach that decouples the memory controller's three primary tasks into three significantly simpler structures that together improve system performance and fairness, especially in integrated CPU-GPU systems. Our three-stage memory controller first groups requests based on row-buffer locality. This grouping allows the second stage to focus only on inter-application request scheduling. These two stages enforce high-level policies regarding performance and fairness, and therefore the last stage consists of simple per-bank FIFO queues (no further command reordering within each bank) and straightforward logic that deals only with low-level DRAM commands and timing. We evaluate the design trade-offs involved in our Staged Memory Scheduler (SMS) and compare it against three state-of-the-art memory controller designs. Our evaluations show that SMS improves CPU performance without degrading GPU frame rate beyond a generally acceptable level, while being significantly less complex to implement than previous application-aware schedulers. Furthermore, SMS can be configured by the system software to prioritize the CPU or the GPU at varying levels to address different performance needs.
Starting Page	416
Ending Page	427
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2366231.2337207
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	40
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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