NDLI: Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures

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Volume 40, Issue 5, December 2012

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Simultaneous branch and warp interweaving for sustained GPU performance

Branch regulation

Tolerating process variations in nanophotonic on-chip networks

Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)

Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures

Reducing memory reference energy with opportunistic virtual caching

Setting an error detection infrastructure with low cost acoustic wave detectors

A case for exploiting subarray-level parallelism (SALP) in DRAM

Physically addressed queueing (PAQ)

Can traditional programming bridge the Ninja performance gap for parallel computing applications?

Configurable fine-grain protection for multicore processor virtualization

Managing distributed ups energy for effective power capping in data centers

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The yin and yang of power and performance for asymmetric hardware and managed software

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Revisiting hardware-assisted page walks for virtualized systems

Scale-out processors

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Buffer-on-board memory systems

Probabilistic shared cache management (PriSM)

The dynamic granularity memory system

Towards energy-proportional datacenter memory with mobile DRAM

Boosting mobile GPU performance with a decoupled access/execute fragment processor

Inspection resistant memory

A case for random shortcut topologies for HPC interconnects

Volume 40, Issue 2, May 2012

Volume 40, Issue 1, March 2012

Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures

Content Provider	ACM Digital Library
Author	Erez, Mattan Krimer, Evgeni Chiang, Patrick
Abstract	A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing speculation, where the pipeline operates at an unsafe voltage with any rare errors detected and resolved by the architecture, has been demonstrated to significantly improve the energy-efficiency of scalar processor designs. Unfortunately, applying the same timing-speculative approach to wide-SIMD architectures, such as those used in highly-efficient GPUs, may not provide similar gains. In this work, we make two important contributions. The first is a set of models describing a parametrized general error probability function that is based on measurements of a fabricated chip and the expected efficiency benefits of timing speculation in a SIMD context. The second contribution is a decoupled SIMD pipeline that more effectively utilizes timing speculation and recovery, when compared with a standard SIMD design that uses only conventional timing speculation. The proposed lane decoupling enables each SIMD lane to tolerate timing errors independent of other adjacent lanes, resulting in higher throughput and improved scalability. We validate our models and evaluate our design using a cycle-based GPU simulator, describe the conditions where efficiency improvements can be obtained, and explore the benefits of decoupling across a wide range of parameters. Our results show that timing speculation can achieve up to 10.3% improvement in efficiency.
Starting Page	237
Ending Page	248
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2366231.2337187
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	40
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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