NDLI: Architecting to achieve a billion requests per second throughput on a single key-value store server platform

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Architecting to achieve a billion requests per second throughput on a single key-value store server platform

Dynamic thread block launch

Volume 43, Issue 1, March 2015

Architecting to achieve a billion requests per second throughput on a single key-value store server platform

Content Provider	ACM Digital Library
Author	Lee, Victor W. Seongil, O. Li, Sheng Kaminsky, Michael Lee, Sukhan Lim, Hyeontaek Kalia, Anuj Ahn, Jung Ho Andersen, David G. Dubey, Pradeep
Abstract	Distributed in-memory key-value stores (KVSs), such as memcached, have become a critical data serving layer in modern Internet-oriented datacenter infrastructure. Their performance and efficiency directly affect the QoS of web services and the efficiency of datacenters. Traditionally, these systems have had significant overheads from inefficient network processing, OS kernel involvement, and concurrency control. Two recent research thrusts have focused upon improving key-value performance. Hardware-centric research has started to explore specialized platforms including FPGAs for KVSs; results demonstrated an order of magnitude increase in throughput and energy efficiency over stock memcached. Software-centric research revisited the KVS application to address fundamental software bottlenecks and to exploit the full potential of modern commodity hardware; these efforts too showed orders of magnitude improvement over stock memcached. We aim at architecting high performance and efficient KVS platforms, and start with a rigorous architectural characterization across system stacks over a collection of representative KVS implementations. Our detailed full-system characterization not only identifies the critical hardware/software ingredients for high-performance KVS systems, but also leads to guided optimizations atop a recent design to achieve a record-setting throughput of 120 million requests per second (MRPS) on a single commodity server. Our implementation delivers 9.2X the performance (RPS) and 2.8X the system energy efficiency (RPS/watt) of the best-published FPGA-based claims. We craft a set of design principles for future platform architectures, and via detailed simulations demonstrate the capability of achieving a billion RPS with a single server constructed following our principles.
Starting Page	476
Ending Page	488
Page Count	13
File Format	PDF
ISSN	01635964
DOI	10.1145/2872887.2750416
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	43
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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