NDLI: Profiling a warehouse-scale computer

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A case for core-assisted bottleneck acceleration in GPUs

Redundant memory mappings for fast access to large memories

Quantitative comparison of hardware transactional memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8

Cost-effective speculative scheduling in high performance processors

Exploring the potential of heterogeneous von neumann/dataflow execution models

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Thermal time shifting

A variable warp size architecture

Manycore network interfaces for in-memory rack-scale computing

Towards sustainable in-situ server systems in the big data era

A scalable processing-in-memory accelerator for parallel graph processing

Profiling a warehouse-scale computer

A fully associative, tagless DRAM cache

LaZy superscalar

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Multiple clone row DRAM

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Branch vanguard

Data reorganization in memory using 3D-stacked DRAM

Flexible software profiling of GPU architectures

Flexible auto-refresh

Semantic locality and context-based prefetching using reinforcement learning

Architecting to achieve a billion requests per second throughput on a single key-value store server platform

Dynamic thread block launch

Volume 43, Issue 1, March 2015

Profiling a warehouse-scale computer

Content Provider	ACM Digital Library
Author	Wei, Gu-Yeon Hazelwood, Kim Brooks, David Ranganathan, Parthasarathy Moseley, Tipp Darago, Juan Pablo Kanev, Svilen
Abstract	With the increasing prevalence of warehouse-scale (WSC) and cloud computing, understanding the interactions of server applications with the underlying microarchitecture becomes ever more important in order to extract maximum performance out of server hardware. To aid such understanding, this paper presents a detailed microarchitectural analysis of live datacenter jobs, measured on more than 20,000 Google machines over a three year period, and comprising thousands of different applications. We first find that WSC workloads are extremely diverse, breeding the need for architectures that can tolerate application variability without performance loss. However, some patterns emerge, offering opportunities for co-optimization of hardware and software. For example, we identify common building blocks in the lower levels of the software stack. This "datacenter tax" can comprise nearly 30% of cycles across jobs running in the fleet, which makes its constituents prime candidates for hardware specialization in future server systems-on-chips. We also uncover opportunities for classic microarchitectural optimizations for server processors, especially in the cache hierarchy. Typical workloads place significant stress on instruction caches and prefer memory latency over bandwidth. They also stall cores often, but compute heavily in bursts. These observations motivate several interesting directions for future warehouse-scale computers.
Starting Page	158
Ending Page	169
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2872887.2750392
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	43
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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