NDLI: Effective ahead pipelining of instruction block address generation

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Temperature-aware microarchitecture

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Banked multiported register files for high-frequency superscalar microprocessors

Transient-fault recovery for chip multiprocessors

A highly configurable cache architecture for embedded systems

Token coherence

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Improving branch prediction by dynamic dataflow-based identification of correlated branches from a large global history

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Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor

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Pipeline damping

Energy efficient co-adaptive instruction fetch and issue

Effective ahead pipelining of instruction block address generation

Dynamically managing the communication-parallelism trade-off in future clustered processors

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Detecting global stride locality in value streams

Overcoming the limitations of conventional vector processors

The Jrpm system for dynamically parallelizing Java programs

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Phase tracking and prediction

Building quantum wires

A performance analysis of PIM, stream processing, and tiled processing on memory-intensive signal processing kernels

Performance analysis of the Alpha 21364-based HP GS1280 multiprocessor

Volume 31, Issue 1, March 2003

Effective ahead pipelining of instruction block address generation

Content Provider	ACM Digital Library
Author	Fraboulet, Antony Seznec, André
Abstract	On a N-way issue superscalar processor, the front end instruction fetch engine must deliver instructions to the execution core at a sustained rate higher than N instructions per cycle. This means that the instruction address generator/predictor (IAG) has to predict the instruction flow at an even higher rate while the prediction accuracy can not be sacrificed.Achieving high accuracy on this prediction becomes more and more critical since the overall pipeline is becoming deeper and deeper with each new generation of processors. Then very complex IAGs featuring different predictors for jumps, returns, conditional and unconditional branches and complex logic are used. Usually, the IAG uses information (branch histories, fetch addresses, . . . ) available at a cycle to predict the next fetch address(es). Unfortunately, a complex IAG cannot deliver a prediction within a short cycle. Therefore, processors rely on a hierarchy of IAGs with increasing accuracies but also increasing latencies: the accurate but slow IAG is used to correct the fast, but less accurate IAG. A significant part of the potential instruction bandwidth is often wasted in pipeline bubbles due to these corrections.As an alternative to the use of a hierarchy of IAGs, it is possible to initiate the instruction address generation several cycles ahead of its use. In this paper, we explore in details such an ahead pipelined IAG. The example illustrated in this paper shows that, even when the instruction address generation is (partially) initiated five cycles ahead of its use, it is possible to reach approximately the same prediction accuracy as the one of a conventional one-block ahead complex IAG. The solution presented in this paper allows to deliver a sustained address generation rate close to one instruction block per cycle with state-of-the art accuracy.
Starting Page	241
Ending Page	252
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/871656.859646
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	31
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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