NDLI: Implicitly-multithreaded processors

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Volume 31, Issue 5, December 2003

Volume 31, Issue 4, Sept 2003

Volume 31, Issue 3, June 2003

Volume 31, Issue 2, May 2003

Temperature-aware microarchitecture

Half-price architecture

Banked multiported register files for high-frequency superscalar microprocessors

Transient-fault recovery for chip multiprocessors

A highly configurable cache architecture for embedded systems

Token coherence

Parallelism in the front-end

Improving dynamic cluster assignment for clustered trace cache processors

A pipelined memory architecture for high throughput network processors

Improving branch prediction by dynamic dataflow-based identification of correlated branches from a large global history

Virtual simple architecture (VISA)

Guided region prefetching

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture

Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor

Implicitly-multithreaded processors

Pipeline damping

Energy efficient co-adaptive instruction fetch and issue

Effective ahead pipelining of instruction block address generation

Dynamically managing the communication-parallelism trade-off in future clustered processors

Efficient use of memory bandwidth to improve network processor throughput

Detecting global stride locality in value streams

Overcoming the limitations of conventional vector processors

The Jrpm system for dynamically parallelizing Java programs

A "flight data recorder" for enabling full-system multiprocessor deterministic replay

Positional adaptation of processors

Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors

Phase tracking and prediction

Building quantum wires

A performance analysis of PIM, stream processing, and tiled processing on memory-intensive signal processing kernels

Performance analysis of the Alpha 21364-based HP GS1280 multiprocessor

Volume 31, Issue 1, March 2003

Implicitly-multithreaded processors

Content Provider	ACM Digital Library
Author	Vijaykumar, T. N. Falsafi, Babak Park, Il
Abstract	This paper proposes the Implicitly-MultiThreaded (IMT) architecture to execute compiler-specified speculative threads on to a modified Simultaneous Multithreading pipeline. IMT reduces hardware complexity by relying on the compiler to select suitable thread spawning points and orchestrate inter-thread register communication. To enhance IMT's effectiveness, this paper proposes three novel microarchitectural mechanisms: (1) resource- and dependence-based fetch policy to fetch and execute suitable instructions, (2) context multiplexing to improve utilization and map as many threads to a single context as allowed by availability of resources, and (3) early threadinvocation to hide thread start-up overhead by overlapping one thread's invocation with other threads' execution.We use SPEC2K benchmarks and cycle-accurate simulation to show that an microarchitecture-optimized IMT improves performance on average by 24% and at best by 69% over an aggressive superscalar. We also compare IMT to two prior proposals, TME and DMT, for speculative threading on an SMT using hardware-extracted threads. Our best IMT design outperforms a comparable TME and DMT on average by 26% and 38% respectively.
Starting Page	39
Ending Page	51
Page Count	13
File Format	PDF
ISSN	01635964
DOI	10.1145/871656.859624
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	31
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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