NDLI: Pipeline damping:a microarchitectural technique to reduce inductive noise in supply voltage

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Banked multiported register files for high-frequency superscalar microprocessors

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Phase tracking and prediction

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A performance analysis of PIM, stream processing, and tiled processing on memory-intensive signal processing kernels

Performance analysis of the Alpha 21364-based HP GS1280 multiprocessor

Volume 31, Issue 1, March 2003

Pipeline damping:a microarchitectural technique to reduce inductive noise in supply voltage

Content Provider	ACM Digital Library
Author	Vijaykumar, T. N. Powell, Michael D.
Abstract	Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause noise margins to decrease, while increasing current and frequency makes supply noise injection larger, especially noise caused by inductance in the supply lines. Creating power distribution systems is one of the key challenges in modern chip design. Decoupling capacitance helps reduce inductance effects, but there is often a peak in the supply impedance that occurs at a resonant frequency caused roughly by the package inductance and the chip decoupling capacitors. This frequency is on the order of 100MHz, which is much lower than the operating frequency of the processor. We propose pipeline damping, an architectural technique which controls instruction issue to guarantee bounds on current variation around the frequency of the supply resonance, thus reducing the resulting supply noise. Damping is a cheaper alternative to expensive, circuit-based noise-reduction techniques. We make the fundamental observation that limiting the current flow change (di) within resonant time period (dt) controls di/dt without large performance loss. Damping guarantees bounds on current variation while allowing processor current to increase or decrease to the magnitude required to maintain performance. Our results show that a damped processor guarantees a 33% reduction in the worst-case current variation with an average performance degradation of 7% and average energy delay of 1.09 compared to an undamped processor.
Starting Page	72
Ending Page	83
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/871656.859628
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	31
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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