NDLI: Improving branch prediction by dynamic dataflow-based identification of correlated branches from a large global history

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Temperature-aware microarchitecture

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Banked multiported register files for high-frequency superscalar microprocessors

Transient-fault recovery for chip multiprocessors

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Token coherence

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Improving dynamic cluster assignment for clustered trace cache processors

A pipelined memory architecture for high throughput network processors

Improving branch prediction by dynamic dataflow-based identification of correlated branches from a large global history

Virtual simple architecture (VISA)

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Phase tracking and prediction

Building quantum wires

A performance analysis of PIM, stream processing, and tiled processing on memory-intensive signal processing kernels

Performance analysis of the Alpha 21364-based HP GS1280 multiprocessor

Volume 31, Issue 1, March 2003

Improving branch prediction by dynamic dataflow-based identification of correlated branches from a large global history

Content Provider	ACM Digital Library
Author	Wilkerson, Chris Stark, Jared Thomas, Renju Franklin, Manoj
Abstract	Deep pipelines and fast clock rates are necessitating the development of high accuracy, multi-stage branch predictors for future processors. Such a predictor uses a collection of predictors, each of which provides its predictions at a different stage of the pipeline front-end. A simple 1-cycle latency line predictor provides predictions in the first stage, followed in a couple of stages later by predictions from a more accurate global predictor. Finally, one or two stages later, a highly accurate corrector predictor selectively corrects the global predictor's prediction. As the corrector predictor has the final say, its accuracy must be very high. The focus of this paper is to propose and evaluate techniques to build high-accuracy corrector predictors.Our techniques rely on using a long global history, and identifying correlated branches in this history by using runtime dataflow information. In particular, we identify for each dynamic branch a set of branches called "affectors", which control the computation that affect that branch's outcome. We propose efficient hardware structures to track dataflow and to identify the affector branches for each dynamic branch; the hardware overhead for identifying affectors for all dynamic branches from a 64 branch global history is only 312 bytes. We then propose two prediction schemes that put to use the affector branch information. Experimental studies show that adding an 8KB corrector predictor (that uses affector information) to a 16KB perceptron predictor (total size 24.2KB) reduces the average misprediction rate for 12 benchmarks from 6.3% to 5.7%, an improvement achieved only by a 64KB perceptron predictor.
Starting Page	314
Ending Page	323
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/871656.859655
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	31
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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