NDLI: Half-price architecture

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Volume 31, Issue 5, December 2003

Volume 31, Issue 4, Sept 2003

Volume 31, Issue 3, June 2003

Volume 31, Issue 2, May 2003

Temperature-aware microarchitecture

Half-price architecture

Banked multiported register files for high-frequency superscalar microprocessors

Transient-fault recovery for chip multiprocessors

A highly configurable cache architecture for embedded systems

Token coherence

Parallelism in the front-end

Improving dynamic cluster assignment for clustered trace cache processors

A pipelined memory architecture for high throughput network processors

Improving branch prediction by dynamic dataflow-based identification of correlated branches from a large global history

Virtual simple architecture (VISA)

Guided region prefetching

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture

Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor

Implicitly-multithreaded processors

Pipeline damping

Energy efficient co-adaptive instruction fetch and issue

Effective ahead pipelining of instruction block address generation

Dynamically managing the communication-parallelism trade-off in future clustered processors

Efficient use of memory bandwidth to improve network processor throughput

Detecting global stride locality in value streams

Overcoming the limitations of conventional vector processors

The Jrpm system for dynamically parallelizing Java programs

A "flight data recorder" for enabling full-system multiprocessor deterministic replay

Positional adaptation of processors

Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors

Phase tracking and prediction

Building quantum wires

A performance analysis of PIM, stream processing, and tiled processing on memory-intensive signal processing kernels

Performance analysis of the Alpha 21364-based HP GS1280 multiprocessor

Volume 31, Issue 1, March 2003

Half-price architecture

Content Provider	ACM Digital Library
Author	Kim, Ilhyun Lipasti, Mikko H.
Abstract	Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for each instruction in structures--such as the register file and wakeup logic--which are often in the processor's critical timing paths. We argue that these structures are overdesigned since only a small fraction of instructions require two source operands to be processed simultaneously. In this paper, we propose the half-price architecture that judiciously removes this overdesign by restricting the processor's capability to handle two source operands in certain timing-critical cases. Two techniques are proposed and evaluated: one for the wakeup logic is sequential wakeup, which decouples half of the tag matching logic from the wakeup bus to reduce the load capacitance of the bus. The other technique for the register file is sequential register access, which halves the register read ports by sequentially accessing two values using a single port when needed. We show that a pipeline that optimizes scheduling and register access for a single operand achieves nearly the same performance as an ideal base machine that fully handles two operands, with 2.2% (worst case 4.8%) IPC degradation.
Starting Page	28
Ending Page	38
Page Count	11
File Format	PDF
ISSN	01635964
DOI	10.1145/871656.859623
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	31
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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