NDLI: Low Power Synthesis and Validation of an Embedded Multiplier for FPGA Based Wireless Communication Systems

Content Provider	Springer Nature Link
Author	Verma, Gaurav Kumar, Manish Khare, Vijay
Copyright Year	2016
Abstract	The advancement in wireless telecommunication technologies like 3G, 4G and now 5G enrich the demand of high performance portable devices, operating at high frequencies i.e. from few hundred MHz to several GHz. High performance can only be achieved at the cost of high power dissipation. Nowadays, the use of FPGAs is rapidly increasing due to its low cost and smaller time to market. Today’s high end FPGAs are capable of implementing high performance designs such as transceivers for RF application, signal processing and image processing applications etc. This is only possible due to their complex designs that includes on chip dedicated multipliers, Dual RAM blocks, Ethernet and DCMs etc. Since FPGAs consume large amount of power, it becomes a challenge for the designers to implement low power battery operated communication systems. Several power estimation models are available in literature for early stage power estimation of FPGAs in the synthesis design flow but they provide less accuracy (high percentage error) for the designs incorporated with low power reduction technique. This paper presents the limitation of existing power estimation model proposed by Deng. The given model is converted into a script using MATLAB. The power values estimated from the power model (script) are compared with the high level synthesis tool: Xpower Analyzer targeted to Virtex FPGA. For estimation of power values, an embedded multiplier is synthesized for two different configurations: one with ‘CE’ (low power) and another without ‘CE’ for different I/O vector length. The results suggested that the given low level power estimation models provide less accuracy (high % error) for the designs incorporated with low power reduction technique i.e. with ‘CE’. Further, there is a scope of remodel the existing model for the observed shortcoming.
Starting Page	365
Ending Page	373
Page Count	9
File Format	PDF
ISSN	09296212
Journal	Wireless Personal Communications
Volume Number	95
Issue Number	2
e-ISSN	1572834X
Language	English
Publisher	Springer US
Publisher Date	2016-11-21
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	IP block Embedded multiplier Power estimation model MATLAB FPGAs Communications Engineering, Networks Signal,Image and Speech Processing Computer Communication Networks
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Computer Science Applications

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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