NDLI: Automatic verification of single-electron transistor arrays based on multiway decision graphs

Content Provider	IET Digital Library
Author	Abed, Sa'ed Ahmad, Imtiaz Shayeji, Mohammad Al Sultan, Sari
Abstract	The single-electron transistor (SET) is considered as a promising alternative to CMOS devices and integrated circuits due to its ultra-low-power consumption. The authors propose an automatic methodology by utilising SET-based multiway decision graph (MDG) for implementing SET architecture. MDG provides a powerful means of abstraction and can be used to manipulate a certain type of first-order logic formula called directed formula (DF). An automatic tool has been developed that is capable of transferring the SET array into MDG DF to generate all paths of all possible reachable states, drawing an abstract diamond-shaped network for the SET array, producing a reduced DF generated by the MDG tool and converting the reduced DF into a conjunctive normal form formula. Then, the authors use the satisfiability approach as a verification engine to verify the correctness of these conversions. The method is tested and verified using MCNC benchmarks. The results outperform approaches based on binary decision diagrams in terms of verification time, number of clauses and variables.
Starting Page	395
Ending Page	404
Page Count	10
ISSN	1751858X
Volume Number	11
e-ISSN	17518598
Issue Number	Issue 4, Jul (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/11/4
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2016.0110
Journal	IET Circuits, Devices & Systems
Publisher Date	2016-12-20
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Automatic Verification Combinatorial Mathematics Conjunctive Normal Form Formula Decision Diagrams Digital Circuit Design, Modelling And Testing Directed Formula First Order Logic Formula Logic And Switching Circuit Logic Array Logic Circuit Logic Design Method Logic Testing Multiway Decision Graph Quantum Interference Device Satisfiability Method Single Electron Transistor Array Single Electron Transistors Ultralow Power Consumption
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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