NDLI: MIPSfpga: using a commercial MIPS soft-core in computer architecture education

Content Provider	IET Digital Library
Author	Harris, Sarah L. Harris, David M. Chaver, Daniel Owen, Robert Kakakhel, Zubair L. Sedano, Enrique Panchul, Yuri Ableidinger, Bruce
Abstract	In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field-programmable gate array (FPGA), making it ideal for both the classroom and research. The supporting materials and labs focus on hands-on learning that emphasises computer architecture, system on chip (SoC) design and hardware–software codesign. Among other things, students learn to set up the MIPS soft-core processor on an FPGA, run and debug programs on the core in simulation and in hardware, add new peripherals to the system, understand the microarchitecture and extend it to support new features, experiment with different cache sizes and content management policies, add new instructions using the CorExtend interface available in MIPS processors, and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.
Starting Page	283
Ending Page	291
Page Count	9
ISSN	1751858X
Volume Number	11
e-ISSN	17518598
Issue Number	Issue 4, Jul (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/11/4
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2016.0383
Journal	IET Circuits, Devices & Systems
Publisher Date	2017-03-07
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Academic Use Cache Sizes Commercial MIPS Soft-core Processor Computer Architecture Computer Architecture Education Computer Science Education Computing Education And Training Content Management Policy CorExtend Interface Digital Circuit Design, Modelling And Testing Education And Training Electronic Engineering Education Field Programmable Gate Array Field-programmable Gate Array Hands-on Learning Hardware-software Codeign Hardware–software Codesign Imagination Technology Learning in AI Learning Material Linux Logic And Switching Circuit Logic Circuit Microprocessor Chips Microprocessors And Microcomputer MIPS MicroAptiv UP Processor MIPSfpga Nonobfuscated RTL Source Code Program Debugging SoC Source Code (software) System on Chip System-on-chip Teaching Infrastructure
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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MIPSfpga: using a commercial MIPS soft-core in computer architecture education

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MIPSfpga: using a commercial MIPS soft-core in computer architecture education