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| Content Provider | IET Digital Library |
|---|---|
| Author | Li, Yanfei Qiao, Ming Jiang, Yongheng Zhou, Xin Xu, Wan Zhang, Bo |
| Abstract | A novel ultra-thin partial silicon-on-insulator (PSOI) LDMOS with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conductivity region for majority carriers to significantly improve the self-heating effect. A combination of uniform and linear variable doping (LVD) profile with highly initial concentration is utilised in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (R on,sp) and breakdown voltage (BV), as well as achieving low power dissipation. With a 60-µm n-drift region length, the NBL PSOI LDMOS obtains a high BV of 940 V with a low maximum temperature (T max) of 327 K at a power (P) of 1 mW/μm, which is reduced by around 56 K in comparison to the conventional SOI LDMOS using an LVD profile for the n-drift region (LVD SOI LDMOS). Moreover, R on,sp of the NBL PSOI LDMOS is lower than that of the LVD SOI LDMOS for a wide range of BV from 400 to 900 V. |
| Starting Page | 1407 |
| Ending Page | 1409 |
| Page Count | 3 |
| ISSN | 00135194 |
| Volume Number | 49 |
| e-ISSN | 1350911X |
| Issue Number | Issue 22, Oct (2013) |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/49/22 |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2013.2220 |
| Journal | Electronics Letters |
| Access Restriction | Open |
| Rights Holder | © The Institution of Engineering and Technology |
| Subject Keyword | Breakdown Voltage Conductivity Region Electric Breakdown Elemental Semiconductor Insulated Gate Field Effect Transistors Linear Variable Doping Ultrathin-PSOI LDMOS LVD Profile Majority Carriers MOSFET N-type Buried Layer N-type Drift Region NBL PSOI LDMOS Power Dissipation Self-heating Effect Semiconductor Doping Silicon-on-insulator Size 60 Mum Specific On-resistance Temperature 327 K Ultrathin-partial Silicon-on-insulator LDMOS Voltage 940 V |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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