NDLI: Fast hardware architecture for grey-level image morphology with flat structuring elements

Content Provider	IET Digital Library
Author	Huitzil, Cesar Torres
Abstract	Mathematical morphology operators, applied in many vision-based applications, are characterised by repetitive operations on large amounts of data. Thus, novel design strategies for efficient hardware implementations are necessary. This study presents and evaluates a real-time hardware architecture for grey-level image erosion and dilation that processes data in streams for an efficient utilisation of memory bandwidth and low on-chip memory requirements. A low-complexity and highly modular architecture is proposed based on a sequence of pipeline stages, and parallel processing in order to minimise computational times. The design is intended to be used as a hardware accelerator in real-time embedded image processing applications requiring moderate-size and non-rectangular flat structuring elements on high-resolution images. The architecture is prototyped on a field programmable gate array device operating at a clock frequency of 260 MHz on a Virtex-6 device which compares favourably to the well-known delay-line-based hardware architectures in terms of complexity, memory requirements and execution time. A 7 × 7 dilation/erosion operator on 1280 × 1024 grey-level image can be performed at a rate of 95 frames per second, but the architecture can be scaled up if required.
Starting Page	112
Ending Page	121
Page Count	10
ISSN	17519659
Volume Number	8
e-ISSN	17519667
Issue Number	Issue 2, Feb (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-ipr/8/2
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-ipr.2013.0224
Journal	IET Image Processing
Publisher Date	2013-10-21
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Clock Frequency Computer Vision Computer Vision And Image Processing Technique Embedded System Erosion Operator Field Programmable Gate Array Fleld Programmable Gate Array Device Frequency 260 MHz Grey-level Image Dilation Grey-level Image Erosion Grey-level Image Morphology High-resolution Image Image Resolution Logic And Switching Circuit Logic Circuit Mathematical Analysis Mathematical Morphology Mathematical Morphology Operators Mathematical Operators Memory Architecture Memory Bandwidth Memory Circuit Moderate-size Flat Structuring Element Modular Architecture Nonrectangular Flat Structuring Element On-chip Memory Requirements Optical, Image And Video Signal Processing Parallel Architecture Parallel Processing Pipeline Processing Pulse Circuit Real-time Embedded Image Processing Real-time Hardware Architecture Virtex-6 Device Vision-based Application
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering Computer Vision and Pattern Recognition Software

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