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High-Resolution Time-to-Digital Converter in Field Programmable Gate Array
| Content Provider | Semantic Scholar |
|---|---|
| Author | Aloisio, Alberto Branchini, Paolo Cicalese, R. Giordano, Raffaele Izzo, Vincenzo Loffredo, Simona Lomoro, R. |
| Copyright Year | 2009 |
| Abstract | Two high-resolution time-interval measuring systems implemented in a SRAM-based FPGA device are presented. The two methods ought to be used for time interpolation within the system clock cycle. We designed and built a PCB hosting a Virtex-5 Xilinx FPGA. We exploited high stability oscillators to test the two different architectures. In the first method, dedicated carry lines are used to perform fine time measurement, while in the second one a differential tapped delay line is used. In this paper we compare the two architectures and show their performance in terms of stability and resolution. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://cds.cern.ch/record/1158663/files/p383.pdf |
| Alternate Webpage(s) | https://cds.cern.ch/record/1158663/files/p383.pdf |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Architecture as Topic Clock signal Converter Device Component Delay Line Device Component Field-programmable gate array Image resolution Interpolation Polychlorinated Biphenyls Printed circuit board Resolution (logic) Static random-access memory Time-to-digital converter |
| Content Type | Text |
| Resource Type | Article |
