NDLI: Memory-efficient SURF architecture for ASIC implementation

Content Provider	IET Digital Library
Author	Lee, Sang Seol Jang, Sung Joon Kim, Jungho Hwang, Youngbae Choi, Byeongho
Abstract	Among the image features for object recognition, speeded up robust features (SURF) have been widely implemented due to their hardware-friendly characteristics and high accuracy. However, because of adopting a fully internal memory-based architecture and a field programmable gate array having large memories for a high performance, most of them are infeasible to the application specific integrated chip (ASIC). A memory-efficient architecture for implementing SURF in ASIC by analysing the characteristics of memory accesses of SURF is presented. In addition, a strategy of dividing an entire image into multiple sub-images, processing them sequentially and overlapping each other to reduce the size of the internal memory while minimising the loss of information is proposed. The proposed architecture was implemented with 767 kb-sized internal memories and 1.2 M logic gates while processing 60 frames per second.
Starting Page	1058
Ending Page	1059
Page Count	2
ISSN	00135194
Volume Number	50
e-ISSN	1350911X
Issue Number	Issue 15, Jul (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/50/15
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2013.4102
Journal	Electronics Letters
Publisher Date	2014-07-08
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Application Specific Integrated Chip Application Specific Integrated Circuit ASIC Computer Vision And Image Processing Technique Field Programmable Gate Array FPGA Hardware-friendly Characteristic Image Feature Image Recognition Information Loss Logic And Switching Circuit Logic Circuit Logic Gate Memory Access Characteristic Memory Architecture Memory-efficient SURF Architecture Multiple Sub-Image Object Recognition Semiconductor Integrated Circuit Speeded Up Robust Feature Storage Capacity 767 Kbit
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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