NDLI: Design of synchronous reference frame phase-locked loop with the presence of dc offsets in the input voltage

Content Provider	IET Digital Library
Author	Kulkarni, Abhijit John, Vinod
Abstract	A novel small-signal state-space model is formulated for the commonly used synchronous reference frame phase-locked loop (SRF-PLL). Using this model, the effect of dc offsets as a function of SRF-PLL design parameters is quantified. It is shown that the unit vectors produced by the phase-locked loop (PLL) will have dc offsets when the input contains dc offsets. This can result in dc injection to the grid, which is highly undesirable. A systematic design method is proposed which ensures that dc injection to the grid is within the prescribed grid interconnection standards. In this design, SRF-PLL bandwidth is analytically computed for different levels of dc offsets in the input. The proposed design is compared with conventional pre-filter-based designs addressing the dc offset issue. The proposed design method results in the fastest transient response for given worst-case input dc offset without changing the PLL structure. Such a design for the SRF-PLL is computationally less intensive and is preferable when low-end digital controllers are used. The analytical results have been verified experimentally.
Starting Page	2435
Ending Page	2443
Page Count	9
ISSN	17554535
Volume Number	8
e-ISSN	17554543
Issue Number	Issue 12, Dec (2015)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-pel/8/12
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-pel.2014.0878
Journal	IET Power Electronics
Publisher Date	2015-12-01
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	DC Injection DC Offset Demodulator Discriminators And Mixers Grid Interconnection Standard Low-end Digital Controller Modulator Phase Locked Loop Power Electronics Power Supply Prefilter-based Design Reference Circuit Small-signal State-Space Model SRF-PLL State Space Method Supervisory Circuit Synchronisation Synchronous Reference Frame Phase Locked Loop Systematic Design Method Transient Response
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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