NDLI: Synchronous reference frame single-phase phase-locked loop (PLL) algorithm based on half-cycle DFT

Content Provider	IET Digital Library
Author	Xia, Tao Zhang, Xu Tan, Guojun Liu, Yezhao
Abstract	In single-phase power and energy applications, sliding discrete Fourier transform (SDFT) filter based quadrature signal generation is a well-known tool for designing advanced phase-locked loops (PLLs), particularly for applications where high disturbance rejection ability is demanded. The SDFT-based PLL, nevertheless, has a limited ability in achieving fast response (a response time more than one cycle of the nominal frequency). To deal with this problem, a synchronous reference frame PLL based on half-cycle DFT (HCDFT) is proposed, enabling a fast and accurate synchronisation even in distorted grid. In this study, the fundamental voltage of the PLL input signal is obtained by a HCDFT filter. Then, phase, frequency and amplitude can be detected by the improved synchronous reference frame phase-locked loop (SRF-PLL). Besides, in order to solve the phase error when the frequency changes, a phase compensator is used. The HCDFT-based SRF-PLL method proposed in this study is compared, through experimental results, with a number of conventional methods, showing that the phase can be estimated under grid voltage disturbances accurately and quickly, which verifies the effectiveness and superiority of the proposed algorithm.
Starting Page	1893
Ending Page	1900
Page Count	8
ISSN	17554535
Volume Number	13
e-ISSN	17554543
Issue Number	Issue 9, Jul (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-pel/13/9
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-pel.2019.1542
Journal	IET Power Electronics
Publisher Date	2020-03-20
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Advanced Phase-locked Loops Control of Electric Power System Demodulator Discrete Fourier Transform Discriminators And Mixers Half-cycle DFT Harmonics HCDFT-based SRF-PLL Method High Disturbance Rejection Ability Improved Synchronous Reference Frame Phase-locked Loop Integral Transforms Modulator Phase Compensator Phase Error Phase Locked Loop PLL Input Signal Power Supply Quality Response Time More Than One Cycle SDFT-based PLL Single-phase Power Synchronisation Synchronous Reference Frame PLL Synchronous Reference Frame Single-phase Phase-locked Loop Algorithm
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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