NDLI: Design of class-EM amplifier with consideration of parasitic non-linear capacitances and on-state resistance

Content Provider	IET Digital Library
Author	Abbasi, Hamed Hayati, Mohsen Kazimierczuk, Marian K. Sekiya, Hiroo
Abstract	In this study, the design of the class-EM power amplifier is presented. In this design, the effects of on-state resistance and non-linear parasitic capacitances of the transistors are investigated. Two metal oxide semiconductor field-effect transistors (MOSFETs) of IRFZ24N and IRF510 with different drain-source resistances are used in the presented circuits. In the given design, the values of the operational frequency and duty ratio are 3.5 MHz and 0.5, respectively. This study shows the importance of considering non-linear parasitic elements of MOSFET, especially drain-source resistance in the designing of the class-EM power amplifiers. It is shown that the class-EM power amplifier with high MOSFET drain-source resistance needs high DC input voltage for both the primary and auxiliary circuits. In the previous works, non-linear on-state resistance and non-linear drain-source and gate-drain capacitances have not been included at the same time in the analyses. Two class-EM amplifiers contain IRF510 and IRFZ24N are designed, simulated, and measured. The efficiency equal to 96.6% with 11.851 W output power at 3.5 MHz and the efficiency equal to 88.4% with 12.361 W output power are achieved for presented class-EM amplifiers contain IRFZ24N and IRF510, respectively.
Starting Page	3065
Ending Page	3071
Page Count	7
ISSN	17554535
Volume Number	13
e-ISSN	17554543
Issue Number	Issue 14, Nov (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-pel/13/14
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-pel.2020.0253
Journal	IET Power Electronics
Publisher Date	2020-06-16
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Amplifiers Analogue Circuit Design Auxiliary Circuit Class-EM Power Amplifier Design Drain-source Resistances Duty Ratio Efficiency 88.4 Percent Efficiency 96.6 Percent Frequency 3.5 MHz Gate-drain Capacitances High DC Input Voltage High MOSFET Drain-source Resistance IRF510 IRFZ24N Metal Oxide Semiconductor Field-effect Transistors Modelling MOSFET Circuit Network Synthesis Nonlinear Capacitances Nonlinear Drain-source Capacitances Nonlinear Parasitic Capacitances On-state Resistance Operational Frequency Power 11.851 W Power 12.361 W Power Amplifier Testing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Analysis and design of class E power amplifier considering MOSFET parasitic input and output capacitances

Design of Class-E Amplifier With MOSFET Linear Gate-to-Drain and Nonlinear Drain-to-Source Capacitances

Effect of gate-to-drain and drain-to-source parasitic capacitances of MOSFET on the performance of Class-E/F3 power amplifier

Analysis and Design of Class-E Power Amplifier With MOSFET Parasitic Linear and Nonlinear Capacitances at Any Duty Ratio

Analysis of Class-DE Amplifier With Linear and Nonlinear Shunt Capacitances at 25% Duty Ratio

Analysis and Design of Class DE Amplifier With Nonlinear Shunt Capacitances

Analysis, Design, and Implementation of the Class-E ZVS Power Amplifier With MOSFET Nonlinear Drain-to-Source Parasitic Capacitance at any Grading Coefficient

High-power multi-octave laterally diffused metal–oxide–semiconductor power amplifier with resistive harmonic termination

5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm2 power area density in 180 nm CMOS process

Design of class-EM amplifier with consideration of parasitic non-linear capacitances and on-state resistance

Similar Documents

Analysis and design of class E power amplifier considering MOSFET parasitic input and output capacitances

Design of Class-E Amplifier With MOSFET Linear Gate-to-Drain and Nonlinear Drain-to-Source Capacitances

Effect of gate-to-drain and drain-to-source parasitic capacitances of MOSFET on the performance of Class-E/F3 power amplifier

Analysis and Design of Class-E Power Amplifier With MOSFET Parasitic Linear and Nonlinear Capacitances at Any Duty Ratio

Analysis of Class-DE Amplifier With Linear and Nonlinear Shunt Capacitances at 25% Duty Ratio

Analysis and Design of Class DE Amplifier With Nonlinear Shunt Capacitances

Analysis, Design, and Implementation of the Class-E ZVS Power Amplifier With MOSFET Nonlinear Drain-to-Source Parasitic Capacitance at any Grading Coefficient

High-power multi-octave laterally diffused metal–oxide–semiconductor power amplifier with resistive harmonic termination

5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm2 power area density in 180 nm CMOS process

Design of class-EM amplifier with consideration of parasitic non-linear capacitances and on-state resistance