NDLI: Failure mechanism for input buffer under CDM test

Content Provider	IET Digital Library
Author	Kao, Tzu Cheng Hung, Chung Yu Lee, Jian Hsing Lien, Chen Hsin Chiu, Chien Wei Lo, Kuo Hsuan Su, Hung Der Weng, Wu Te
Abstract	The influence of the body layout on the charged device model (CDM) failure site and the robustness of the input buffer is explored. The failure analysis results confirm that the gate oxide is damaged. The failure site can be moved from the region above the channel to the overlap region between the source and the gate once the body layout is cut from a ring into a small segment, providing direct evidence demonstrating that the CDM current flows through the gate oxide via the body and the source of the transistor, since both connect to the V ss bus line. Otherwise, changing the body layout of the input buffer transistor does not vary the failure location.
Starting Page	667
Ending Page	669
Page Count	3
ISSN	00135194
Volume Number	50
e-ISSN	1350911X
Issue Number	Issue 9, Apr (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/50/9
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2013.4094
Journal	Electronics Letters
Publisher Date	2014-04-22
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Body Layout Influence Buffer Circuit CDM Current Flow CDM Testing Charged Device Model Design And Testing Electric Charge Electrostatics Equivalent Circuit Failure Analysis Failure Mechanism Analysis Gate Oxide Input Buffer Transistor Integrated Circuit Reliability Integrated Circuit Testing Layout Modelling And Testing Reliability Semiconductor Device Modelling Semiconductor Device Reliability Semiconductor Integrated Circuit Design Transistor Vss Bus Line
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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