NDLI: Stability improvement of amorphous InGaZnO TFTs by an asymmetric design

Content Provider	IET Digital Library
Author	Hsu, Chih Chieh Wu, Chien Hsun Ting, Wei Chieh
Abstract	In this reported work, amorphous InGaZnO thin film transistors (TFTs) with symmetric and asymmetric structures are fabricated. A constant positive gate bias for a time of 1–5 × 104 s was then applied to the TFTs to investigate their performance variation. The mobilities of the TFTs were not significantly degraded by a long stress time of 5 × 104 s. Also, decreases of sub-threshold swing and off-state current were observed for a stress time of 104 s. Although significant threshold voltage variation was found for the a-IGZO TFT with a symmetric design during the stress test, it could be reduced by 56% for the TFT fabricated by the proposed asymmetric design.
Starting Page	1534
Ending Page	1536
Page Count	3
ISSN	00135194
Volume Number	51
e-ISSN	1350911X
Issue Number	Issue 19, Sep (2015)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/51/19
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2015.2036
Journal	Electronics Letters
Publisher Date	2015-09-07
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Amorphous IGZO TFT Amorphous Semiconductors Asymmetric Design Constant Positive Gate Bias Design And Testing Equivalent Circuit Field Effect Device Gallium Compound Indium Compound InGaZnO Off-state Current Semiconductor Device Modelling Semiconductor Device Testing Stability Improvement Stress Test Subthreshold Swing Ternary SemiConductor Thin Film Transistor Thin Film Transistors Threshold Voltage Variation Zinc Compound
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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