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| Content Provider | IET Digital Library |
|---|---|
| Author | Torres, L. C. B. Castro, C. L. Coelho, F. Torres, F. Sill Braga, A. P. |
| Abstract | A new learning method for classification problems that is suitable for integrated circuit implementation is presented. The method, which outperforms current approaches in many data sets, is based on a structural description of the learning set represented by a planar graph. The final classification function is composed of a hierarchical mixture of local experts, which yields a large margin classifier for the whole learning set. Since it is based only on distance calculations, on-chip learning can also be executed. The method is also appropriate for online and incremental learning, since model parameters are obtained directly from the data set, without need of user interaction for learning. |
| Starting Page | 1967 |
| Ending Page | 1969 |
| Page Count | 3 |
| ISSN | 00135194 |
| Volume Number | 51 |
| e-ISSN | 1350911X |
| Issue Number | Issue 24, Nov (2015) |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/51/24 |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2015.1644 |
| Journal | Electronics Letters |
| Access Restriction | Open |
| Rights Holder | © The Institution of Engineering and Technology |
| Subject Keyword | Data Set Distance-based Large Margin Classifier Electronic Engineering Computing Incremental Learning Integrated Circuit Design Knowledge Engineering Technique Layout Learning in AI Learning Method Modelling And Testing On-chip Learning Online Learning Planar Graph Semiconductor Integrated Circuit Design |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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