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| Content Provider | IET Digital Library |
|---|---|
| Author | Ismail, A. Nafarawi, M. El |
| Abstract | A novel energy-efficient 8 bit 2.78 kS/s capacitance-to-digital converter (CDC) interface for capacitive pressure sensors is presented. A new direct-capacitance-comparison technique (DCCT) is proposed and employed together with a successive approximation register (SAR) algorithm to resolve the sensor capacitance by, directly, comparing it with an on-chip binary-weighted capacitive digital-to-analogue converter (DAC) array. An offset DAC array compensates for the sensor rest and parasitic capacitances, accordingly, the interface gives a dynamically zoomed digital-output code that corresponds only to the sensor capacitance change. The full-scale input capacitance of the CDC is easily adjustable to interface to a wide range of sensors. The proposed 8 bit SAR-based CDC is designed and simulated using 0.18 μm standard CMOS technology. The CDC exhibits a capacitance sensing range from 4 to 6 pF, provides a resolution and linearity of 7.26 and 8.2 bit, respectively. It achieves a figure-of-merit of 1.8 pJ/step at 1.4 V supply and 36 μs conversion time. Compared with the state-of-the-art implementations with similar performance. |
| Starting Page | 2007 |
| Ending Page | 2009 |
| Page Count | 3 |
| ISSN | 00135194 |
| Volume Number | 51 |
| e-ISSN | 1350911X |
| Issue Number | Issue 24, Nov (2015) |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/51/24 |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2015.2435 |
| Journal | Electronics Letters |
| Access Restriction | Open |
| Rights Holder | © The Institution of Engineering and Technology |
| Subject Keyword | A/D And D/A Convertor Capacitance 4 PF to 6 PF Capacitance Measurement Capacitance-to-digital Converter Interface Capacitive Pressure Sensor Capacitive Sensor CDC Interface CMOS Integrated Circuit CMOS Technology Digital-analogue Conversion Direct-capacitance-comparison Technique Energy-efficient Successive Approximation Register Full-scale Input Parasitic Capacitance Impedance And Admittance Measurement Integrated Circuit Design Layout Modelling And Testing Offset DAC Array Onchip Binary-weighted Capacitive Digital-to-analogue Converter Array Power 7.7 MuW Pressure And Vacuum Measurement Pressure Sonsor SAR Algorithm Semiconductor Integrated Circuit Design Sensing Device And Transducers Size 0.18 Mum Successive Approximation Register Algorithm Time 36 Mus Voltage 1.4 V Word Length 7.26 Bit Word Length 8 Bit Word Length 8.2 Bit |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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