NDLI: Near-threshold all-digital PLL with dynamic voltage scaling power management

Content Provider	IET Digital Library
Author	Chang, C. W. Chang, K. Y. Chu, Y. H. Jou, S. J.
Abstract	A near-threshold all-digital phase-locked loop (ADPLL) with a power management unit (PMU) is presented to make the proposed ADPLL work reliably across variations and power consumption as well is reduced. When operated under near-threshold condition from 0.52 to 0.58 V V DD, the gated digitally controlled oscillator frequency range is from 90.8 to 245.7 MHz. When the ADPLL is operated at 0.52 V V DD, a lock-in time of 9.5 μs at 100 MHz output clock frequency is measured with an rms period jitter of 0.17% UI. With the PMU, the ADPLL power reduction at 130 MHz output frequency is 39% and the buck converter power consumption is nearly 30 μW. Consequently, the proposed ADPLL with PMU is suitable to event-driven or low-voltage applications.
Starting Page	109
Ending Page	111
Page Count	3
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 2, Jan (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/2
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2015.2672
Journal	Electronics Letters
Publisher Date	2015-11-27
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	ADPLL Buck Converter Demodulator Digital Circuit Digital Phase Locked Loops Digitally Controlled Oscillator Discriminators And Mixers Dynamic Voltage Scaling Power Management Event Driven Application Modulator Near-threshold All-digital Phase-locked Loop Near-threshold All-digital PLL Oscillator Performance Evaluation And Testing PMU Power Aware Computing Power Consumption Power Converter Power Electronics Power Management Unit Power Supply Supervisory Circuit Voltage 0.52 V to 0.58 V
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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